forked from M-Labs/artiq-zynq
use openocd files from zynq-rs
This commit is contained in:
parent
4dfd82f6ec
commit
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16
local_run.sh
16
local_run.sh
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@ -21,19 +21,21 @@ done
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load_bitstream_cmd=""
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cd openocd
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build_dir=`pwd`/build
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result_dir=`pwd`/result
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cd $OPENOCD_ZYNQ
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if [ $impure -eq 1 ]; then
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if [ $load_bitstream -eq 1 ]; then
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load_bitstream_cmd="-g ../build/gateware/top.bit"
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load_bitstream_cmd="-g $build_dir/gateware/top.bit"
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fi
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openocd -f zc706.cfg -c "load_image ../build/firmware/armv7-none-eabihf/debug/szl; resume 0; exit"
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openocd -f zc706.cfg -c "load_image $build_dir/firmware/armv7-none-eabihf/debug/szl; resume 0; exit"
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sleep 5
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artiq_netboot $load_bitstream_cmd -f ../build/runtime.bin -b $board_host
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artiq_netboot $load_bitstream_cmd -f $build_dir/runtime.bin -b $board_host
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else
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if [ $load_bitstream -eq 1 ]; then
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load_bitstream_cmd="-g ../result/top.bit"
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load_bitstream_cmd="-g $result_dir/top.bit"
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fi
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openocd -f zc706.cfg -c "load_image ../result/szl.elf; resume 0; exit"
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openocd -f zc706.cfg -c "load_image $result_dir/szl.elf; resume 0; exit"
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sleep 5
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artiq_netboot $load_bitstream_cmd -f ../result/runtime.bin -b $board_host
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artiq_netboot $load_bitstream_cmd -f $result_dir/runtime.bin -b $board_host
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fi
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@ -1,40 +0,0 @@
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source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
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adapter_khz 1000
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set PL_TAPID 0x23731093
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set SMP 1
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source ./zynq-7000.cfg
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reset_config srst_only srst_open_drain
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adapter_nsrst_assert_width 250
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adapter_nsrst_delay 400
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc xc7_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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pld device virtex2 zynq.tap 1
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init
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xc7_program zynq.tap
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reset halt
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# Disable MMU
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targets $_TARGETNAME_1
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arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
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targets $_TARGETNAME_0
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arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
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@ -1,95 +0,0 @@
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#
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# Xilinx Zynq 7000 SoC
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#
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# Chris Johns <chrisj@rtems.org>
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#
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# Setup
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# -----
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#
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# Create a user configuration following the "Configuration Basics" in the user
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# documentation. In the file have:
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#
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# source [find interface/ftdi/flyswatter2.cfg]
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# source [find board/zynq-zc706-eval.cfg]
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# adapter_khz 2000
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# init
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#
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if { [info exists CHIPNAME] } {
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global _CHIPNAME
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set _CHIPNAME $CHIPNAME
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} else {
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global _CHIPNAME
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set _CHIPNAME zynq
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a bigendian
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set _ENDIAN little
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}
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if { [info exists SMP] } {
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global _SMP
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set _SMP 1
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} else {
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global _SMP
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set _SMP 0
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}
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#
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# PL Tap.
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#
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# See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed.
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# 0x03731093 - ZC706 Eval board 1.1
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# 0x23731093 - ??
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# 0x23727093 - Zedboard Rev. C and D
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#
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# Set in your configuration file or board specific file.
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#
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if { [info exists PL_TAPID] } {
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set _PL_TAPID $PL_TAPID
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} else {
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set _PL_TAPID 0x03731093
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}
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jtag newtap $_CHIPNAME tap -irlen 6 -ircapture 0x001 -irmask 0x003 \
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-expected-id $_PL_TAPID
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#
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# CoreSight Debug Access Port
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#
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x4ba00477
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x03 \
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-expected-id $_DAP_TAPID
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#
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# GDB target: Cortex-A9, using DAP, configuring only one core
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# Base addresses of cores:
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# core 0 - 0xF8890000
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# core 1 - 0xF8892000
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#
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# Read from the ROM table with the patch to read the nested table.
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#
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set _TARGETNAME_0 $_CHIPNAME.cpu.0
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set _TARGETNAME_1 $_CHIPNAME.cpu.1
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target create $_TARGETNAME_0 cortex_a -coreid 0 \
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-endian $_ENDIAN \
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-chain-position $_CHIPNAME.dap \
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-dbgbase 0x80090000
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if { $_SMP } {
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echo "Zynq CPU1."
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target create $_TARGETNAME_1 cortex_a -coreid 1 \
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-endian $_ENDIAN \
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-chain-position $_CHIPNAME.dap \
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-dbgbase 0x80092000
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target smp $_TARGETNAME_0 $_TARGETNAME_1
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}
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@ -36,7 +36,7 @@ load_bitstream_cmd=""
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echo "Creating $target_folder..."
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ssh $sshopts $target_host "mkdir -p $target_folder"
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echo "Copying files..."
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rsync -e "ssh $sshopts" openocd/* $target_host:$target_folder
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rsync -e "ssh $sshopts" $OPENOCD_ZYNQ/* $target_host:$target_folder
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if [ $impure -eq 1 ]; then
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if [ $load_bitstream -eq 1 ]; then
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load_bitstream_cmd="-g build/gateware/top.bit"
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@ -1,6 +1,7 @@
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let
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pkgs = import <nixpkgs> { overlays = [ (import ./mozilla-overlay.nix) ]; };
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artiq-fast = <artiq-fast>;
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zynq-rs = (import ./zynq-rs.nix { inherit pkgs; });
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rustPlatform = (import ./rustPlatform.nix { inherit pkgs; });
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artiqpkgs = import "${artiq-fast}/default.nix" { inherit pkgs; };
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vivado = import "${artiq-fast}/vivado.nix" { inherit pkgs; };
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@ -28,4 +29,5 @@ in
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];
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XARGO_RUST_SRC = "${rustPlatform.rust.rustc.src}/src";
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OPENOCD_ZYNQ = "${zynq-rs}/openocd";
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}
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@ -0,0 +1,7 @@
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{ pkgs }:
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pkgs.fetchgit {
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url = "https://git.m-labs.hk/M-Labs/zynq-rs.git";
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rev = "4e18368aaf59c29e703d5ecae6c0eb93ef89c2d2";
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sha256 = "0jfnjn76pfq5wp6qnxhkqmvldv02cy60wyp1ikaj9n47p69cabj8";
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}
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