forked from M-Labs/artiq-zynq
updated zynq-rs and IRQ handling
This commit is contained in:
parent
c2a6fb72f7
commit
bb65074254
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@ -20,7 +20,7 @@ let
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name = "firmware";
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name = "firmware";
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src = ./src;
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src = ./src;
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cargoSha256 = "1h6zm7kq1f24kyjgmmmq7b9jydvs23glsrfij6s86nlwbhd5xrcb";
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cargoSha256 = "1d84yknyizbxgsqj478339fxcyvxq9pzdv0ljrwrgmzgfynqmssj";
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nativeBuildInputs = [
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nativeBuildInputs = [
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pkgs.gnumake
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pkgs.gnumake
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@ -56,7 +56,7 @@ checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
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[[package]]
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[[package]]
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name = "core_io"
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name = "core_io"
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version = "0.1.20200410"
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version = "0.1.20200410"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#6e6612bc3e12e50b4f6e61cde47100c3d4ab982a"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
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dependencies = [
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dependencies = [
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"memchr",
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"memchr",
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]
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]
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@ -186,7 +186,7 @@ dependencies = [
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[[package]]
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[[package]]
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name = "libasync"
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name = "libasync"
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version = "0.0.0"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#6e6612bc3e12e50b4f6e61cde47100c3d4ab982a"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
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dependencies = [
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dependencies = [
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"embedded-hal",
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"embedded-hal",
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"libcortex_a9",
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"libcortex_a9",
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@ -198,7 +198,7 @@ dependencies = [
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[[package]]
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[[package]]
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name = "libboard_zynq"
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name = "libboard_zynq"
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version = "0.0.0"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#6e6612bc3e12e50b4f6e61cde47100c3d4ab982a"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
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dependencies = [
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dependencies = [
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"bit_field",
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"bit_field",
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"embedded-hal",
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"embedded-hal",
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@ -223,7 +223,7 @@ dependencies = [
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[[package]]
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[[package]]
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name = "libconfig"
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name = "libconfig"
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version = "0.1.0"
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version = "0.1.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#6e6612bc3e12e50b4f6e61cde47100c3d4ab982a"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
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dependencies = [
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dependencies = [
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"core_io",
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"core_io",
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"fatfs",
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"fatfs",
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@ -234,7 +234,7 @@ dependencies = [
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[[package]]
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[[package]]
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name = "libcortex_a9"
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name = "libcortex_a9"
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version = "0.0.0"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#6e6612bc3e12e50b4f6e61cde47100c3d4ab982a"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
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dependencies = [
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dependencies = [
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"bit_field",
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"bit_field",
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"libregister",
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"libregister",
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@ -250,7 +250,7 @@ checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
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[[package]]
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[[package]]
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name = "libregister"
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name = "libregister"
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version = "0.0.0"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#6e6612bc3e12e50b4f6e61cde47100c3d4ab982a"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
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dependencies = [
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dependencies = [
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"bit_field",
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"bit_field",
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"vcell",
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"vcell",
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@ -260,7 +260,7 @@ dependencies = [
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[[package]]
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[[package]]
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name = "libsupport_zynq"
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name = "libsupport_zynq"
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version = "0.0.0"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#6e6612bc3e12e50b4f6e61cde47100c3d4ab982a"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
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dependencies = [
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dependencies = [
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"cc",
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"cc",
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"compiler_builtins",
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"compiler_builtins",
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@ -69,4 +69,18 @@ SECTIONS
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. += 0x20000;
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. += 0x20000;
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__stack0_start = .;
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__stack0_start = .;
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} > SDRAM
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} > SDRAM
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.irq_stack1 (NOLOAD) : ALIGN(8)
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{
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__irq_stack1_end = .;
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. += 0x100;
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__irq_stack1_start = .;
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} > SDRAM
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.irq_stack0 (NOLOAD) : ALIGN(8)
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{
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__irq_stack0_end = .;
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. += 0x100;
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__irq_stack0_start = .;
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} > SDRAM
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}
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}
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@ -1,10 +1,10 @@
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use libboard_zynq::{gic, mpcore, println, stdio};
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use libboard_zynq::{gic, mpcore, println, stdio};
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use libcortex_a9::{
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use libcortex_a9::{
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asm,
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asm, interrupt_handler,
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regs::{MPIDR, SP},
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regs::MPIDR,
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spin_lock_yield, notify_spin_lock
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spin_lock_yield, notify_spin_lock
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};
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};
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use libregister::{RegisterR, RegisterW};
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use libregister::RegisterR;
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use core::sync::atomic::{AtomicBool, Ordering};
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use core::sync::atomic::{AtomicBool, Ordering};
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extern "C" {
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extern "C" {
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@ -14,50 +14,31 @@ extern "C" {
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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#[link_section = ".text.boot"]
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interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn IRQ() {
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asm!(
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// setup SP, depending on CPU 0 or 1
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"mrc p15, #0, r0, c0, c0, #5",
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"movw r1, :lower16:__stack0_start",
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"movt r1, :upper16:__stack0_start",
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"tst r0, #3",
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"movwne r1, :lower16:__stack1_start",
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"movtne r1, :upper16:__stack1_start",
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"mov sp, r1",
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"bl __IRQ",
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options(noreturn)
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);
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}
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#[no_mangle]
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pub unsafe extern "C" fn __IRQ() {
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if MPIDR.read().cpu_id() == 1 {
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if MPIDR.read().cpu_id() == 1 {
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mut gic = gic::InterruptController::gic(mpcore);
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let mut gic = gic::InterruptController::gic(mpcore);
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let id = gic.get_interrupt_id();
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let id = gic.get_interrupt_id();
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if id.0 == 0 {
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if id.0 == 0 {
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gic.end_interrupt(id);
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gic.end_interrupt(id);
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// save the SP and set it back after exiting IRQ
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// exception unwinding expect to unwind from this function, as this is not the entrance
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// function, maybe to IRQ which cannot further unwind...
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// if we set the SP to __stack1_start, interesting exceptions would be triggered when
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// we try to unwind the stack...
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let v = SP.read();
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asm::exit_irq();
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asm::exit_irq();
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SP.write(v);
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asm!("b core1_restart");
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asm::enable_irq();
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CORE1_RESTART.store(false, Ordering::Relaxed);
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notify_spin_lock();
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main_core1();
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}
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}
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}
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}
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stdio::drop_uart();
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stdio::drop_uart();
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println!("IRQ");
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println!("IRQ");
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loop {}
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loop {}
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}
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});
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// This is actually not an interrupt handler, just use the macro for convenience.
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// This function would be called in normal mode (instead of interrupt mode), the outer naked
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// function wrapper is to tell libunwind to stop when it reaches here.
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interrupt_handler!(core1_restart, core1_restart_impl, __stack0_start, __stack1_start, {
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asm::enable_irq();
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CORE1_RESTART.store(false, Ordering::Relaxed);
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notify_spin_lock();
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main_core1();
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});
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pub fn restart_core1() {
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pub fn restart_core1() {
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
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@ -3,6 +3,6 @@ let
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in
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in
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pkgs.fetchgit {
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pkgs.fetchgit {
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url = "https://git.m-labs.hk/M-Labs/zynq-rs.git";
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url = "https://git.m-labs.hk/M-Labs/zynq-rs.git";
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rev = "6e6612bc3e12e50b4f6e61cde47100c3d4ab982a";
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rev = "78d58d17ec7906a6cadd1678576939d20612cf8f";
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sha256 = "14hj77n9g2zack6sjgs7337j8yq9r3jrpdsmc62kmxfbbmy8jhlg";
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sha256 = "1y74i7j9kawhlq22zyicjsxldx9f7h4i22yabw1z4qga19zv6qjd";
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}
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}
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