forked from M-Labs/artiq-zynq
drtio: increase robustness for longer payloads
This commit is contained in:
parent
4a34777b97
commit
b76f634686
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@ -19,6 +19,46 @@ impl From<IoError> for Error {
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}
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}
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#[derive(PartialEq, Clone, Copy, Debug)]
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#[repr(u8)]
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pub enum PayloadStatus {
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Middle = 0,
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First = 1,
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Last = 2,
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FirstAndLast = 3,
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}
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impl From<u8> for PayloadStatus {
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fn from(value: u8) -> PayloadStatus {
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match value {
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0 => PayloadStatus::Middle,
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1 => PayloadStatus::First,
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2 => PayloadStatus::Last,
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3 => PayloadStatus::FirstAndLast,
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_ => unreachable!(),
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}
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}
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}
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impl PayloadStatus {
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pub fn is_first(self) -> bool {
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self == PayloadStatus::First || self == PayloadStatus::FirstAndLast
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}
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pub fn is_last(self) -> bool {
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self == PayloadStatus::Last || self == PayloadStatus::FirstAndLast
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}
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pub fn from_status(first: bool, last: bool) -> PayloadStatus {
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match (first, last) {
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(true, true) => PayloadStatus::FirstAndLast,
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(true, false) => PayloadStatus::First,
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(false, true) => PayloadStatus::Last,
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(false, false) => PayloadStatus::Middle,
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}
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}
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}
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#[derive(PartialEq, Debug)]
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pub enum Packet {
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EchoRequest,
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@ -159,7 +199,7 @@ pub enum Packet {
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DmaAddTraceRequest {
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destination: u8,
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id: u32,
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last: bool,
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status: PayloadStatus,
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length: u16,
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trace: [u8; MASTER_PAYLOAD_MAX_SIZE],
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},
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@ -192,7 +232,7 @@ pub enum Packet {
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SubkernelAddDataRequest {
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destination: u8,
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id: u32,
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last: bool,
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status: PayloadStatus,
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length: u16,
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data: [u8; MASTER_PAYLOAD_MAX_SIZE],
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},
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@ -228,7 +268,7 @@ pub enum Packet {
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SubkernelMessage {
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destination: u8,
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id: u32,
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last: bool,
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status: PayloadStatus,
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length: u16,
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data: [u8; MASTER_PAYLOAD_MAX_SIZE],
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},
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@ -391,14 +431,14 @@ impl Packet {
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0xb0 => {
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let destination = reader.read_u8()?;
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let id = reader.read_u32()?;
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let last = reader.read_bool()?;
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let status = PayloadStatus::from(reader.read_u8()?);
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let length = reader.read_u16()?;
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let mut trace: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
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reader.read_exact(&mut trace[0..length as usize])?;
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Packet::DmaAddTraceRequest {
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destination: destination,
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id: id,
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last: last,
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status: status,
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length: length as u16,
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trace: trace,
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}
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@ -432,14 +472,14 @@ impl Packet {
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0xc0 => {
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let destination = reader.read_u8()?;
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let id = reader.read_u32()?;
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let last = reader.read_bool()?;
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let status = PayloadStatus::from(reader.read_u8()?);
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let length = reader.read_u16()?;
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let mut data: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
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reader.read_exact(&mut data[0..length as usize])?;
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Packet::SubkernelAddDataRequest {
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destination: destination,
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id: id,
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last: last,
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status: status,
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length: length as u16,
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data: data,
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}
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@ -482,14 +522,14 @@ impl Packet {
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0xcb => {
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let destination = reader.read_u8()?;
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let id = reader.read_u32()?;
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let last = reader.read_bool()?;
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let status = PayloadStatus::from(reader.read_u8()?);
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let length = reader.read_u16()?;
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let mut data: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
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reader.read_exact(&mut data[0..length as usize])?;
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Packet::SubkernelMessage {
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destination: destination,
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id: id,
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last: last,
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status: status,
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length: length as u16,
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data: data,
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}
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@ -713,14 +753,14 @@ impl Packet {
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Packet::DmaAddTraceRequest {
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destination,
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id,
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last,
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status,
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trace,
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length,
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} => {
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writer.write_u8(0xb0)?;
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writer.write_u8(destination)?;
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writer.write_u32(id)?;
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writer.write_bool(last)?;
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writer.write_u8(status as u8)?;
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// trace may be broken down to fit within drtio aux memory limit
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// will be reconstructed by satellite
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writer.write_u16(length)?;
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@ -771,14 +811,14 @@ impl Packet {
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Packet::SubkernelAddDataRequest {
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destination,
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id,
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last,
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status,
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data,
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length,
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} => {
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writer.write_u8(0xc0)?;
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writer.write_u8(destination)?;
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writer.write_u32(id)?;
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writer.write_bool(last)?;
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writer.write_u8(status as u8)?;
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writer.write_u16(length)?;
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writer.write_all(&data[0..length as usize])?;
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}
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@ -822,14 +862,14 @@ impl Packet {
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Packet::SubkernelMessage {
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destination,
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id,
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last,
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status,
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data,
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length,
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} => {
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writer.write_u8(0xcb)?;
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writer.write_u8(destination)?;
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writer.write_u32(id)?;
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writer.write_bool(last)?;
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writer.write_u8(status as u8)?;
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writer.write_u16(length)?;
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writer.write_all(&data[0..length as usize])?;
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}
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@ -13,8 +13,10 @@ pub mod drtio {
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use ksupport::{resolve_channel_name, ASYNC_ERROR_BUSY, ASYNC_ERROR_COLLISION, ASYNC_ERROR_SEQUENCE_ERROR,
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SEEN_ASYNC_ERRORS};
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use libasync::{delay, task};
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use libboard_artiq::{drtioaux::Error, drtioaux_async, drtioaux_async::Packet,
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drtioaux_proto::MASTER_PAYLOAD_MAX_SIZE};
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use libboard_artiq::{drtioaux::Error,
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drtioaux_async,
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drtioaux_async::Packet,
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drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE}};
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use libboard_zynq::time::Milliseconds;
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use log::{error, info, warn};
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@ -61,11 +63,11 @@ pub mod drtio {
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Packet::SubkernelMessage {
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id,
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destination: from,
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last,
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status,
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length,
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data,
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} => {
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subkernel::message_handle_incoming(id, last, length as usize, &data).await;
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subkernel::message_handle_incoming(id, status, length as usize, &data).await;
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// acknowledge receiving part of the message
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let _lock = aux_mutex.async_lock().await;
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drtioaux_async::send(linkno, &Packet::SubkernelMessageAck { destination: from })
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@ -463,7 +465,7 @@ pub mod drtio {
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reply_handler_f: HandlerF,
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) -> Result<(), &'static str>
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where
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PacketF: Fn(&[u8; MASTER_PAYLOAD_MAX_SIZE], bool, usize) -> Packet,
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PacketF: Fn(&[u8; MASTER_PAYLOAD_MAX_SIZE], PayloadStatus, usize) -> Packet,
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HandlerF: Fn(&Packet) -> Result<(), &'static str>,
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{
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let mut i = 0;
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@ -474,10 +476,12 @@ pub mod drtio {
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} else {
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data.len() - i
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} as usize;
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let first = i == 0;
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let last = i + len == data.len();
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slice[..len].clone_from_slice(&data[i..i + len]);
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i += len;
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let packet = packet_f(&slice, last, len);
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let status = PayloadStatus::from_status(first, last);
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let packet = packet_f(&slice, status, len);
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let reply = aux_transact(aux_mutex, linkno, &packet, timer).await?;
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reply_handler_f(&reply)?;
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}
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@ -498,10 +502,10 @@ pub mod drtio {
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aux_mutex,
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timer,
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trace,
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|slice, last, len| Packet::DmaAddTraceRequest {
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|slice, status, len| Packet::DmaAddTraceRequest {
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id: id,
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destination: destination,
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last: last,
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status: status,
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length: len as u16,
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trace: *slice,
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},
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@ -655,10 +659,10 @@ pub mod drtio {
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aux_mutex,
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timer,
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data,
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|slice, last, len| Packet::SubkernelAddDataRequest {
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|slice, status, len| Packet::SubkernelAddDataRequest {
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id: id,
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destination: destination,
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last: last,
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status: status,
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length: len as u16,
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data: *slice,
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},
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@ -742,10 +746,10 @@ pub mod drtio {
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aux_mutex,
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timer,
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message,
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|slice, last, len| Packet::SubkernelMessage {
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|slice, status, len| Packet::SubkernelMessage {
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destination: destination,
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id: id,
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last: last,
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status: status,
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length: len as u16,
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data: *slice,
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},
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@ -1,6 +1,6 @@
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use alloc::{collections::btree_map::BTreeMap, vec::Vec};
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use libboard_artiq::pl::csr;
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use libboard_artiq::{drtioaux_proto::PayloadStatus, pl::csr};
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use libcortex_a9::cache::dcci_slice;
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const ALIGNMENT: usize = 64;
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@ -50,10 +50,10 @@ impl Manager {
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}
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}
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pub fn add(&mut self, id: u32, last: bool, trace: &[u8], trace_len: usize) -> Result<(), Error> {
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pub fn add(&mut self, id: u32, status: PayloadStatus, trace: &[u8], trace_len: usize) -> Result<(), Error> {
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let entry = match self.entries.get_mut(&id) {
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Some(entry) => {
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if entry.complete {
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if entry.complete || status.is_first() {
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// replace entry
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self.entries.remove(&id);
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self.entries.insert(
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@ -83,7 +83,7 @@ impl Manager {
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};
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entry.trace.extend(&trace[0..trace_len]);
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if last {
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if status.is_last() {
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entry.trace.push(0);
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let data_len = entry.trace.len();
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@ -162,7 +162,7 @@ fn process_aux_packet(
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&drtioaux::Packet::SubkernelMessage {
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destination: destination,
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id: kernel_manager.get_current_id().unwrap(),
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last: meta.last,
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status: meta.status,
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length: meta.len as u16,
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data: data_slice,
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},
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@ -494,12 +494,12 @@ fn process_aux_packet(
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drtioaux::Packet::DmaAddTraceRequest {
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destination: _destination,
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id,
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last,
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status,
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length,
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trace,
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} => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = dma_manager.add(id, last, &trace, length as usize).is_ok();
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let succeeded = dma_manager.add(id, status, &trace, length as usize).is_ok();
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drtioaux::send(0, &drtioaux::Packet::DmaAddTraceReply { succeeded: succeeded })
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}
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drtioaux::Packet::DmaRemoveTraceRequest {
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@ -527,12 +527,12 @@ fn process_aux_packet(
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drtioaux::Packet::SubkernelAddDataRequest {
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destination: _destination,
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id,
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last,
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status,
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length,
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data,
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} => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = kernel_manager.add(id, last, &data, length as usize).is_ok();
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let succeeded = kernel_manager.add(id, status, &data, length as usize).is_ok();
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drtioaux::send(0, &drtioaux::Packet::SubkernelAddDataReply { succeeded: succeeded })
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}
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drtioaux::Packet::SubkernelLoadRunRequest {
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@ -562,7 +562,7 @@ fn process_aux_packet(
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drtioaux::send(
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0,
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&drtioaux::Packet::SubkernelException {
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last: meta.last,
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last: meta.status.is_last(),
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length: meta.len,
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data: data_slice,
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},
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@ -571,12 +571,12 @@ fn process_aux_packet(
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drtioaux::Packet::SubkernelMessage {
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destination,
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id: _id,
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last,
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status,
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length,
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data,
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} => {
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forward!(_routing_table, destination, *_rank, _repeaters, &packet, timer);
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kernel_manager.message_handle_incoming(last, length as usize, &data);
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kernel_manager.message_handle_incoming(status, length as usize, &data);
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drtioaux::send(
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0,
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&drtioaux::Packet::SubkernelMessageAck {
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@ -596,7 +596,7 @@ fn process_aux_packet(
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&drtioaux::Packet::SubkernelMessage {
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destination: *_rank,
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id: kernel_manager.get_current_id().unwrap(),
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last: meta.last,
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status: meta.status,
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length: meta.len as u16,
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data: data_slice,
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},
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