forked from M-Labs/artiq-zynq
dma: fix endianness issues
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a9f725dd33
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@ -6,14 +6,7 @@ from migen_axi.interconnect import axi
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from artiq.gateware.rtio.analyzer import message_len, MessageEncoder
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def convert_endianness(signal):
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assert len(signal) % 8 == 0
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nbytes = len(signal)//8
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signal_bytes = []
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for i in range(nbytes):
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signal_bytes.append(signal[8*i:8*(i+1)])
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return Cat(*reversed(signal_bytes))
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import endianness
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class AXIDMAWriter(Module, AutoCSR):
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@ -64,7 +57,7 @@ class AXIDMAWriter(Module, AutoCSR):
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membus.w.id.eq(0),
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membus.w.valid.eq(self.sink.stb),
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self.sink.ack.eq(membus.w.ready),
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membus.w.data.eq(convert_endianness(self.sink.data)),
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membus.w.data.eq(endianness.convert_signal(self.sink.data)),
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membus.w.strb.eq(2**(dw//8)-1),
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]
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beat_count = Signal(max=burst_length)
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@ -6,6 +6,8 @@ from migen_axi.interconnect import axi
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from artiq.gateware.rtio.dma import RawSlicer, RecordConverter, RecordSlicer, TimeOffset, CRIMaster
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import endianness
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AXI_BURST_LEN = 16
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@ -50,7 +52,7 @@ class AXIReader(Module):
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self.comb += [
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self.source.stb.eq(membus.r.valid),
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membus.r.ready.eq(self.source.ack),
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self.source.data.eq(membus.r.data),
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self.source.data.eq(endianness.convert_signal(membus.r.data)),
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# Note that when eop_pending=1, no new transactions are made and inflight_cnt is no longer incremented
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self.source.eop.eq(eop_pending & membus.r.last & (inflight_cnt == 1))
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]
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@ -0,0 +1,21 @@
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from migen import *
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def convert_signal(signal):
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assert len(signal) % 8 == 0
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nbytes = len(signal)//8
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signal_bytes = []
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for i in range(nbytes):
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signal_bytes.append(signal[8*i:8*(i+1)])
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return Cat(*reversed(signal_bytes))
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def convert_value(value, size):
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assert size % 8 == 0
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nbytes = size//8
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result = 0
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for i in range(nbytes):
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result <<= 8
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result |= value & 0xff
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value >>= 8
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return result
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@ -10,6 +10,7 @@ from artiq.gateware import rtio
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from artiq.gateware.rtio import cri
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from artiq.gateware.rtio.phy import ttl_simple
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import endianness
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import dma
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@ -47,6 +48,7 @@ class AXIMemorySim:
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data = self.data[addr]
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else:
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data = 0
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data = endianness.convert_value(data, len(self.bus.r.data))
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yield from self.bus.write_r(request.id, data, last=i == request_len-1)
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else:
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yield
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