forked from M-Labs/artiq-zynq
kasli_soc: fix acpki import
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4856cddb65
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716a5924d1
@ -24,7 +24,7 @@ from artiq.gateware.wrpll import wrpll
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import dma
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import analyzer
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import acpki
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import acpki as acpki_lib
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import drtio_aux_controller
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import zynq_clocking
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from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
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@ -184,10 +184,10 @@ class GenericStandalone(SoCCore):
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if self.acpki:
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.config["KI_IMPL"] = "csr"
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@ -349,10 +349,10 @@ class GenericMaster(SoCCore):
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if self.acpki:
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.config["KI_IMPL"] = "csr"
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@ -544,10 +544,10 @@ class GenericSatellite(SoCCore):
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if self.acpki:
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.config["KI_IMPL"] = "csr"
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