diff --git a/flake.nix b/flake.nix index 1d2f7049..e5421f35 100644 --- a/flake.nix +++ b/flake.nix @@ -11,6 +11,7 @@ zynqpkgs = zynq-rs.packages.x86_64-linux; artiqpkgs = artiq.packages.x86_64-linux; llvmPackages_11 = zynq-rs.llvmPackages_11; + zynqRev = self.sourceInfo.rev or "unknown"; rust = zynq-rs.rust; rustPlatform = zynq-rs.rustPlatform; @@ -137,6 +138,7 @@ llvmPackages_11.clang-unwrapped ]; buildPhase = '' + export ZYNQ_REV=${zynqRev} export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library" export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include" export CARGO_HOME=$(mktemp -d cargo-home.XXX) @@ -164,6 +166,7 @@ ]; } '' + export ZYNQ_REV=${zynqRev} python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json} mkdir -p $out $out/nix-support cp build/top.bit $out @@ -386,6 +389,7 @@ binutils-arm pre-commit ]; + ZYNQ_REV="${zynqRev}"; XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library"; CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"; ZYNQ_RS = "${zynq-rs}"; diff --git a/src/gateware/config.py b/src/gateware/config.py index 78f97a45..f13475c1 100644 --- a/src/gateware/config.py +++ b/src/gateware/config.py @@ -1,5 +1,15 @@ +import os +from artiq._version import get_version from misoc.integration import cpu_interface + +def generate_ident(variant): + return "{}+{};{}".format( + get_version().split(".")[0], + os.getenv("ZYNQ_REV", default="unknown")[:8], + variant, + ) + def write_csr_file(soc, filename): with open(filename, "w") as f: f.write(cpu_interface.get_csr_rust( diff --git a/src/gateware/ebaz4205.py b/src/gateware/ebaz4205.py index d64d2e18..26e6c464 100644 --- a/src/gateware/ebaz4205.py +++ b/src/gateware/ebaz4205.py @@ -7,7 +7,7 @@ import dma from artiq.gateware import rtio from artiq.gateware.rtio.phy import spi2, ttl_simple from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path -from config import write_csr_file, write_mem_file, write_rustc_cfg_file +from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file from migen import * from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal from migen.build.platforms import ebaz4205 @@ -125,7 +125,7 @@ class EBAZ4205(SoCCore): "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]" ) - ident = self.__class__.__name__ + ident = generate_ident(self.__class__.__name__) if self.acpki: ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 98d6f415..2f00adea 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -27,7 +27,7 @@ import analyzer import acpki import drtio_aux_controller import zynq_clocking -from config import write_csr_file, write_mem_file, write_rustc_cfg_file +from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file eem_iostandard_dict = { 0: "LVDS_25", @@ -115,7 +115,7 @@ class GenericStandalone(SoCCore): platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", ]) - ident = description["variant"] + ident = generate_ident(description["variant"]) if self.acpki: ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) @@ -229,7 +229,7 @@ class GenericMaster(SoCCore): platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", ]) - ident = description["variant"] + ident = generate_ident(description["variant"]) if self.acpki: ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) @@ -438,7 +438,7 @@ class GenericSatellite(SoCCore): platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", ]) - ident = description["variant"] + ident = generate_ident(description["variant"]) if self.acpki: ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 395d6c66..6acc98d8 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -25,7 +25,7 @@ import analyzer import acpki import drtio_aux_controller import zynq_clocking -from config import write_csr_file, write_mem_file, write_rustc_cfg_file +from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file class SMAClkinForward(Module): def __init__(self, platform): @@ -130,7 +130,7 @@ class ZC706(SoCCore): platform = zc706.Platform() prepare_zc706_platform(platform) - ident = self.__class__.__name__ + ident = generate_ident(self.__class__.__name__) if self.acpki: ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) @@ -203,7 +203,7 @@ class _MasterBase(SoCCore): platform = zc706.Platform() prepare_zc706_platform(platform) - ident = self.__class__.__name__ + ident = generate_ident(self.__class__.__name__) if self.acpki: ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) @@ -344,7 +344,7 @@ class _SatelliteBase(SoCCore): platform = zc706.Platform() prepare_zc706_platform(platform) - ident = self.__class__.__name__ + ident = generate_ident(self.__class__.__name__) if self.acpki: ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)