From 07044752b6677213285c58be47b48f36f916a262 Mon Sep 17 00:00:00 2001 From: linuswck Date: Mon, 6 Nov 2023 12:24:44 +0800 Subject: [PATCH] zynq_clocking: add ext_async_rst to AsyncRstSYNCR --- src/gateware/zynq_clocking.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index d94b1bc0..553a43fa 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -65,7 +65,7 @@ class ClockSwitchFSM(Module): class SYSCRG(Module, AutoCSR): - def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6): + def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6, ext_async_rst=None): # assumes bootstrap clock is same freq as main and sys output self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -125,10 +125,19 @@ class SYSCRG(Module, AutoCSR): Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=mmcm_clk208, o_O=self.cd_clk200.clk), - AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked), - AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked), ] + if ext_async_rst is not None: + self.specials += [ + AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked | ext_async_rst), + AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked | ext_async_rst), + ] + else: + self.specials += [ + AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked), + AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked), + ] + reset_counter = Signal(4, reset=15) ic_reset = Signal(reset=1) self.sync.clk200 += \