forked from M-Labs/artiq-zynq
runtime/main: removed bitstream loading code
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eb78e4e2da
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050b2457a4
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@ -14,14 +14,14 @@ extern crate alloc;
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use core::{cmp, str};
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use log::{info, warn, error};
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use libboard_zynq::{timer::GlobalTimer, devc, slcr, mpcore, gic};
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use libboard_zynq::{timer::GlobalTimer, mpcore, gic, slcr};
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use libasync::{task, block_async};
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use libsupport_zynq::ram;
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use libregister::RegisterW;
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use nb;
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use void::Void;
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use embedded_hal::blocking::delay::DelayMs;
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use libconfig::{Config, load_pl};
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use libconfig::Config;
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use libregister::RegisterW;
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mod proto_core_io;
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mod proto_async;
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@ -65,22 +65,6 @@ fn init_gateware() {
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slcr::FpgaRstCtrl::zeroed()
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);
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});
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if devc::DevC::new().is_done() {
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info!("gateware already loaded");
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// Do not load again: assume that the gateware already present is
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// what we want (e.g. gateware configured via JTAG before PS
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// startup, or by FSBL).
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// Make sure that the PL/PS interface is enabled (e.g. OpenOCD does not enable it).
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.init_postload_fpga();
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});
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} else {
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// Load from SD card
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match load_pl::load_bitstream_from_sd() {
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Ok(_) => info!("Bitstream loaded successfully!"),
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Err(e) => info!("Failure loading bitstream: {}", e),
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}
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}
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}
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fn identifier_read(buf: &mut [u8]) -> &str {
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@ -193,7 +177,6 @@ pub fn main_core0() {
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init_gateware();
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info!("detected gateware: {}", identifier_read(&mut [0; 64]));
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let cfg = match Config::new() {
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Ok(cfg) => cfg,
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Err(err) => {
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