forked from M-Labs/artiq-zynq
libconfig/load_pl: added alignment for devc buffer
According to the TRM, the buffer should be 64B aligned. Without the alignment would cause failure for the DMA transaction. It seems that the allocator would give some alignment, but to be more correct we should specify that with the alloc interface.
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@ -140,16 +140,23 @@ pub fn load_bitstream<File: Read + Seek>(
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file: &mut File,
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file: &mut File,
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) -> Result<(), PlLoadingError> {
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) -> Result<(), PlLoadingError> {
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let size = locate_bitstream(file)?;
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let size = locate_bitstream(file)?;
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let mut buffer: alloc::vec::Vec<u8> = alloc::vec::Vec::with_capacity(size);
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unsafe {
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unsafe {
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buffer.set_len(buffer.capacity());
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// align to 64 bytes
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let ptr = alloc::alloc::alloc(alloc::alloc::Layout::from_size_align(size, 64).unwrap());
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let buffer = core::slice::from_raw_parts_mut(ptr, size);
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file.read_exact(buffer).map_err(|e| {
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core::ptr::drop_in_place(ptr);
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e
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})?;
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let mut devcfg = devc::DevC::new();
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devcfg.enable();
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devcfg.program(&buffer).map_err(|e| {
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core::ptr::drop_in_place(ptr);
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e
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})?;
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core::ptr::drop_in_place(ptr);
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Ok(())
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}
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}
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file.read_exact(&mut buffer)?;
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let mut devcfg = devc::DevC::new();
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devcfg.enable();
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devcfg.program(&buffer)?;
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Ok(())
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}
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}
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pub fn load_bitstream_from_sd() -> Result<(), PlLoadingError> {
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pub fn load_bitstream_from_sd() -> Result<(), PlLoadingError> {
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