forked from M-Labs/artiq-zynq
RTIO DMA: Compiled but not working.
* Cache flush should be done before playback instead when getting the handler. * `csr::rtio_dma::enable_read()` would loop forever, probably bug in the gateware.
This commit is contained in:
parent
64dad88a32
commit
0310421085
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@ -12,7 +12,11 @@ device_db = {
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"target": "cortexa9"
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}
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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# led? are common to all variants
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"led0": {
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"type": "local",
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@ -0,0 +1,26 @@
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from artiq.experiment import *
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class DMAPulses(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("core_dma")
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self.setattr_device("led0")
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@kernel
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def record(self):
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with self.core_dma.record("pulses"):
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# all RTIO operations now go to the "pulses"
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# DMA buffer, instead of being executed immediately.
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self.led0.pulse(100*ns)
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delay(100*ns)
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@kernel
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def run(self):
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self.core.reset()
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self.record()
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# prefetch the address of the DMA buffer
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# for faster playback trigger
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pulses_handle = self.core_dma.get_handle("pulses")
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self.core.break_realtime()
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self.core_dma.playback_handle(pulses_handle)
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@ -96,6 +96,7 @@ dependencies = [
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name = "dyld"
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version = "0.1.0"
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dependencies = [
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"libcortex_a9",
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"log",
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]
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@ -8,3 +8,5 @@ name = "dyld"
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[dependencies]
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log = "0.4"
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libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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@ -2,6 +2,7 @@
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extern crate alloc;
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extern crate log;
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extern crate libcortex_a9;
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use core::{convert, fmt, str};
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use alloc::string::String;
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@ -7,6 +7,10 @@ use super::{
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image::Image,
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Library,
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};
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use libcortex_a9::{
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cache::{dcci_slice, iciallu, bpiall},
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asm::{dsb, isb},
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};
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pub trait Relocatable {
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fn offset(&self) -> usize;
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@ -154,6 +158,13 @@ pub fn rebind(
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_ => {}
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}
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}
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// FIXME: the cache maintainance operations may be more than enough,
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// may cause performance degradation.
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dcci_slice(lib.image.data);
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iciallu();
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bpiall();
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dsb();
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isb();
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Ok(())
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}
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@ -3,6 +3,7 @@ use libm;
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use crate::eh_artiq;
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use crate::rtio;
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use super::rpc::{rpc_send, rpc_send_async, rpc_recv};
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use super::dma;
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macro_rules! api {
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($i:ident) => ({
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@ -50,6 +51,13 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
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api!(rtio_input_timestamped_data = rtio::input_timestamped_data),
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api!(rtio_log = rtio::log),
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// rtio dma
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api!(dma_record_start = dma::dma_record_start),
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api!(dma_record_stop = dma::dma_record_stop),
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api!(dma_erase = dma::dma_erase),
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api!(dma_retrieve = dma::dma_retrieve),
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api!(dma_playback = dma::dma_playback),
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// Double-precision floating-point arithmetic helper functions
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// RTABI chapter 4.1.2, Table 2
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api!(__aeabi_dadd),
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@ -16,8 +16,10 @@ use crate::eh_artiq;
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use super::{
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api::resolve,
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rpc::rpc_send_async,
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dma::init_dma,
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CHANNEL_0TO1, CHANNEL_1TO0,
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KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0,
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KERNEL_LIBRARY,
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Message,
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};
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@ -93,6 +95,10 @@ impl KernelImage {
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})
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}
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pub fn get_library_ptr(&mut self) -> *mut Library {
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&mut self.library as *mut Library
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}
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pub unsafe fn exec(&mut self) {
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// Flush data cache entries for the image in DDR, including
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// Memory/Instruction Synchronization Barriers
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@ -118,6 +124,9 @@ pub fn main_core1() {
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enable_fpu();
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debug!("FPU enabled on Core1");
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init_dma();
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debug!("Init DMA!");
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let mut core1_tx = None;
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while core1_tx.is_none() {
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core1_tx = CHANNEL_1TO0.lock().take();
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@ -139,9 +148,10 @@ pub fn main_core1() {
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let result = dyld::load(&data, &resolve)
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.and_then(KernelImage::new);
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match result {
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Ok(kernel) => {
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Ok(mut kernel) => {
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unsafe {
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KERNEL_LOAD_ADDR = kernel.library.image.as_ptr() as usize;
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KERNEL_LIBRARY = kernel.get_library_ptr();
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}
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loaded_kernel = Some(kernel);
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debug!("kernel loaded");
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@ -0,0 +1,300 @@
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use crate::{
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pl::csr,
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artiq_raise,
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rtio,
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};
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use alloc::{vec::Vec, string::String, collections::BTreeMap, str};
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use cslice::CSlice;
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use super::KERNEL_LIBRARY;
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use core::mem;
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use log::debug;
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use libcortex_a9::{
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cache::dcci_slice,
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asm::dsb,
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};
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const ALIGNMENT: usize = 16 * 8;
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const DMA_BUFFER_SIZE: usize = 16 * 8 * 1024;
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struct DmaRecorder {
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active: bool,
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data_len: usize,
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buffer: [u8; DMA_BUFFER_SIZE],
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}
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static mut DMA_RECORDER: DmaRecorder = DmaRecorder {
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active: false,
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data_len: 0,
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buffer: [0; DMA_BUFFER_SIZE],
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};
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#[derive(Debug)]
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struct Entry {
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trace: Vec<u8>,
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padding_len: usize,
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duration: u64
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}
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#[derive(Debug)]
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pub struct Manager {
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entries: BTreeMap<String, Entry>,
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recording_name: String,
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recording_trace: Vec<u8>
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}
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// Copied from https://github.com/m-labs/artiq/blob/master/artiq/firmware/runtime/rtio_dma.rs
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// basically without modification except removing some warnings.
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impl Manager {
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pub fn new() -> Manager {
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Manager {
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entries: BTreeMap::new(),
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recording_name: String::new(),
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recording_trace: Vec::new(),
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}
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}
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pub fn record_start(&mut self, name: &str) {
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self.recording_name = String::from(name);
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self.recording_trace = Vec::new();
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// or we could needlessly OOM replacing a large trace
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self.entries.remove(name);
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}
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pub fn record_append(&mut self, data: &[u8]) {
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self.recording_trace.extend_from_slice(data);
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}
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pub fn record_stop(&mut self, duration: u64) {
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let mut trace = Vec::new();
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mem::swap(&mut self.recording_trace, &mut trace);
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trace.push(0);
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let data_len = trace.len();
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// Realign.
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trace.reserve(ALIGNMENT - 1);
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let padding = ALIGNMENT - trace.as_ptr() as usize % ALIGNMENT;
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let padding = if padding == ALIGNMENT { 0 } else { padding };
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for _ in 0..padding {
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// Vec guarantees that this will not reallocate
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trace.push(0)
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}
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for i in 1..data_len + 1 {
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trace[data_len + padding - i] = trace[data_len - i]
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}
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let mut name = String::new();
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mem::swap(&mut self.recording_name, &mut name);
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self.entries.insert(name, Entry {
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trace, duration,
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padding_len: padding,
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});
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}
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pub fn erase(&mut self, name: &str) {
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self.entries.remove(name);
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}
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pub fn with_trace<F, R>(&self, name: &str, f: F) -> R
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where F: FnOnce(Option<&[u8]>, u64) -> R {
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match self.entries.get(name) {
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Some(entry) => f(Some(&entry.trace[entry.padding_len..]), entry.duration),
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None => f(None, 0)
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}
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}
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}
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static mut DMA_MANAGER: Option<Manager> = None;
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#[repr(C)]
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pub struct DmaTrace {
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duration: i64,
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address: i32,
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}
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pub fn init_dma() {
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unsafe {
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DMA_MANAGER = Some(Manager::new());
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}
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}
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fn dma_record_flush() {
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unsafe {
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let manager = DMA_MANAGER.as_mut().unwrap();
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manager.record_append(&DMA_RECORDER.buffer[..DMA_RECORDER.data_len]);
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DMA_RECORDER.data_len = 0;
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}
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}
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pub extern fn dma_record_start(name: CSlice<u8>) {
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let name = str::from_utf8(name.as_ref()).unwrap();
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unsafe {
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if DMA_RECORDER.active {
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artiq_raise!("DMAError", "DMA is already recording")
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}
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let library = KERNEL_LIBRARY.as_mut().unwrap();
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library.rebind(b"rtio_output",
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dma_record_output as *const ()).unwrap();
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library.rebind(b"rtio_output_wide",
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dma_record_output_wide as *const ()).unwrap();
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DMA_RECORDER.active = true;
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let manager = DMA_MANAGER.as_mut().unwrap();
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manager.record_start(name);
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}
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}
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pub extern fn dma_record_stop(duration: i64) {
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unsafe {
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dma_record_flush();
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if !DMA_RECORDER.active {
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artiq_raise!("DMAError", "DMA is not recording")
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}
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let library = KERNEL_LIBRARY.as_mut().unwrap();
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library.rebind(b"rtio_output",
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rtio::output as *const ()).unwrap();
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library.rebind(b"rtio_output_wide",
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rtio::output_wide as *const ()).unwrap();
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DMA_RECORDER.active = false;
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let manager = DMA_MANAGER.as_mut().unwrap();
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manager.record_stop(duration as u64);
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}
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}
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#[inline(always)]
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unsafe fn dma_record_output_prepare(timestamp: i64, target: i32,
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words: usize) -> &'static mut [u8] {
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// See gateware/rtio/dma.py.
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const HEADER_LENGTH: usize = /*length*/1 + /*channel*/3 + /*timestamp*/8 + /*address*/1;
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let length = HEADER_LENGTH + /*data*/words * 4;
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if DMA_RECORDER.buffer.len() - DMA_RECORDER.data_len < length {
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dma_record_flush()
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}
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let record = &mut DMA_RECORDER.buffer[DMA_RECORDER.data_len..
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DMA_RECORDER.data_len + length];
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DMA_RECORDER.data_len += length;
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let (header, data) = record.split_at_mut(HEADER_LENGTH);
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header.copy_from_slice(&[
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(length >> 0) as u8,
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(target >> 8) as u8,
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(target >> 16) as u8,
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(target >> 24) as u8,
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(timestamp >> 0) as u8,
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(timestamp >> 8) as u8,
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(timestamp >> 16) as u8,
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(timestamp >> 24) as u8,
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(timestamp >> 32) as u8,
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(timestamp >> 40) as u8,
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(timestamp >> 48) as u8,
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(timestamp >> 56) as u8,
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(target >> 0) as u8,
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]);
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data
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}
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pub extern fn dma_record_output(target: i32, word: i32) {
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unsafe {
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let timestamp = csr::rtio::now_read() as i64;
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let data = dma_record_output_prepare(timestamp, target, 1);
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data.copy_from_slice(&[
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(word >> 0) as u8,
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(word >> 8) as u8,
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(word >> 16) as u8,
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(word >> 24) as u8,
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]);
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}
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}
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pub extern fn dma_record_output_wide(target: i32, words: CSlice<i32>) {
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assert!(words.len() <= 16); // enforce the hardware limit
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unsafe {
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let timestamp = csr::rtio::now_read() as i64;
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let mut data = dma_record_output_prepare(timestamp, target, words.len());
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for word in words.as_ref().iter() {
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data[..4].copy_from_slice(&[
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(word >> 0) as u8,
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(word >> 8) as u8,
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(word >> 16) as u8,
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(word >> 24) as u8,
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]);
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data = &mut data[4..];
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}
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}
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}
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pub extern fn dma_erase(name: CSlice<u8>) {
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let name = str::from_utf8(name.as_ref()).unwrap();
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let manager = unsafe {
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DMA_MANAGER.as_mut().unwrap()
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};
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manager.erase(name);
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}
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pub extern fn dma_retrieve(name: CSlice<u8>) -> DmaTrace {
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let name = str::from_utf8(name.as_ref()).unwrap();
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let manager = unsafe {
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DMA_MANAGER.as_mut().unwrap()
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};
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let (trace, duration) = manager.with_trace(name, |trace, duration| (trace.map(|v| {
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dcci_slice(v);
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dsb();
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v.as_ptr()
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}), duration));
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match trace {
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Some(ptr) => Ok(DmaTrace {
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address: ptr as i32,
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duration: duration as i64,
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}),
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None => Err(())
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}.unwrap_or_else(|_| {
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artiq_raise!("DMAError", "DMA trace not found");
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})
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}
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pub extern fn dma_playback(timestamp: i64, ptr: i32) {
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assert!(ptr % ALIGNMENT as i32 == 0);
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debug!("DMA Playback");
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unsafe {
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csr::rtio_dma::base_address_write(ptr as u32);
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csr::rtio_dma::time_offset_write(timestamp as u64);
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csr::cri_con::selected_write(1);
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csr::rtio_dma::enable_write(1);
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while csr::rtio_dma::enable_read() != 0 {}
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csr::cri_con::selected_write(0);
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let error = csr::rtio_dma::error_read();
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if error != 0 {
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let timestamp = csr::rtio_dma::error_timestamp_read();
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let channel = csr::rtio_dma::error_channel_read();
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csr::rtio_dma::error_write(1);
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if error & 1 != 0 {
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artiq_raise!("RTIOUnderflow",
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"RTIO underflow at {0} mu, channel {1}",
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timestamp as i64, channel as i64, 0);
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}
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if error & 2 != 0 {
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artiq_raise!("RTIODestinationUnreachable",
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"RTIO destination unreachable, output, at {0} mu, channel {1}",
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timestamp as i64, channel as i64, 0);
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}
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}
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}
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}
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@ -1,6 +1,7 @@
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use core::ptr;
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use alloc::{vec::Vec, sync::Arc, string::String};
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use dyld::Library;
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use libcortex_a9::{mutex::Mutex, sync_channel};
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use crate::eh_artiq;
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@ -9,6 +10,7 @@ pub use control::Control;
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pub mod core1;
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mod api;
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mod rpc;
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mod dma;
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#[derive(Debug)]
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pub struct RPCException {
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|
@ -39,3 +41,5 @@ static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<Message>>> = Mutex::new(N
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static mut KERNEL_CHANNEL_0TO1: *mut () = ptr::null_mut();
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static mut KERNEL_CHANNEL_1TO0: *mut () = ptr::null_mut();
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static mut KERNEL_LIBRARY: *mut Library = ptr::null_mut();
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