6a1854f18b
flake: update dependencies
763df7d869
msys2: update
85173d4e70
remove scipy from artiq dependencies
5e1fcbdce2
Update flake and msys2 packages
32e512e10d
flake: update dependencies
9e85187ead
flake: update dependencies
25ee3c68f1
wand: remove (no qt6)
7f00ab0cb6
update conda, py3.12
d5c99474ed
linien: py3.12
1e64b5786c
msys2: update, qt6
2e1de17bbf
flake: update dependencies
648dc4283c
update dependencies
50a8eb02c0
flake: update dependencies
54df981af2
flake: update dependencies
4880eacaed
update anaconda
move
follows
to top-level inputs
Explicit inputs instead of nested
follows
16af931d0c
dax: reenable tests
9cd19ede46
use flake for dax
153ac853e9
flake: update dependencies
5f87f3a59d
artiq: update
5c51937450
lda: update
Flake (and version bump) for DAX
2ae839f61a
flake: update
9c5fc66a0a
README: msys2
7df7aae25c
linien: py3.10
ef56a6ddb6
flake: update dependencies
166655b6d2
flake: update dependencies
188954ddc7
zynq_us: clocks (WIP)
0f2376410f
zynq_us/slcr: add type enums for clksel fields
2e5f7ec2f7
zynq_us/slcr: make `unlocked` method a trait
c2455b1cda
zynq_us/slcr: add crl_apb definitions
3b1d6e090e
zynq_us/slcr: add crl_apb definitions
1e50f68f41
zynq_us/slcr: move common register types to their own file
70489132fb
libregister: add macro for multi-bit RO fields
c3273a6ff8
[nfc]zynq_us/slcr: rename pll regs
20784803f0
zync_us: add lib.rs
2b3045b46c
zync_us: start defining SLCR blocks
2c179841be
zynq_us/uart: same register fields as zynq, just a different location
508fac66e8
add crate for ultrascale+ drivers
3a6517b8db
libboard_zynq/uart: re-export regs and baudgen for use in US+
c7a5c2cf00
Cargo: add libcortex_r5
6a5fd192df
libcortex_a9: make functions public for use with r5
ddc184cd89
libcortex_r5: add lib.rs
efa9a17cd2
libcortex_r5: add cache control functions
4b139cfc2f
libcortex_r5: add register definitions