From ff96bf903befc255814e083c77da619af2b19a9b Mon Sep 17 00:00:00 2001 From: Astro Date: Wed, 6 Nov 2019 23:04:35 +0100 Subject: [PATCH] zynq::ddr: only enable_ddr if no clock yet that's only an issue for the cora z7 --- src/zynq/ddr/mod.rs | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/zynq/ddr/mod.rs b/src/zynq/ddr/mod.rs index fba49f9..282c114 100644 --- a/src/zynq/ddr/mod.rs +++ b/src/zynq/ddr/mod.rs @@ -36,8 +36,11 @@ impl DdrRam { /// 10.6.1 DDR Clock Initialization fn clock_setup() -> CpuClocks { let clocks = CpuClocks::get(); - CpuClocks::enable_ddr(clocks.arm); + if clocks.ddr == 0 { + CpuClocks::enable_ddr(clocks.arm); + } let clocks = CpuClocks::get(); + println!("Clocks: {:?}", clocks); let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8; let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;