From ee7ae7f7cc27c7017df9eb1a5e3e6b0b35597c33 Mon Sep 17 00:00:00 2001 From: Astro Date: Thu, 30 May 2019 00:23:31 +0200 Subject: [PATCH] slcr: add soft_rst() --- src/slcr.rs | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/slcr.rs b/src/slcr.rs index fe135f1..9ebd38a 100644 --- a/src/slcr.rs +++ b/src/slcr.rs @@ -66,7 +66,7 @@ pub struct RegisterBlock { reserved2: [u32; 5], pub clk_621_true: RW, reserved3: [u32; 14], - pub pss_rst_ctrl: RW, + pub pss_rst_ctrl: PssRstCtrl, pub ddr_rst_ctrl: RW, pub topsw_rst_ctrl: RW, pub dmac_rst_ctrl: RW, @@ -207,6 +207,16 @@ impl RegisterBlock { self_.slcr_lock.lock(); r } + + /// Perform a soft reset + pub fn soft_reset(&mut self) -> ! { + self.pss_rst_ctrl.write( + PssRstCtrl::zeroed() + .soft_rst(true) + ); + + unreachable!() + } } register!(slcr_lock, SlcrLock, WO, u32); @@ -305,6 +315,9 @@ impl UartRstCtrl { } } +register!(pss_rst_ctrl, PssRstCtrl, RW, u32); +register_bit!(pss_rst_ctrl, soft_rst, 1); + /// Used for MioPin*.io_type #[repr(u8)] pub enum IoBufferType {