From ceeaa6427e7032be1dab97fe329cccda1077e58d Mon Sep 17 00:00:00 2001 From: Astro Date: Mon, 28 Oct 2019 23:58:25 +0100 Subject: [PATCH] zynq::ddr: fix typo --- src/zynq/ddr/mod.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/zynq/ddr/mod.rs b/src/zynq/ddr/mod.rs index e9504df..c981cfb 100644 --- a/src/zynq/ddr/mod.rs +++ b/src/zynq/ddr/mod.rs @@ -36,7 +36,7 @@ impl DdrRam { /// 10.6.1 DDR Clock Initialization fn clock_setup() -> CpuClocks { let clocks = CpuClocks::get(); - CpuClocks::enable_ddr(clocks.cpu); + CpuClocks::enable_ddr(clocks.arm); let clocks = CpuClocks::get(); let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;