From c3273a6ff898886f6661f40dcb3327cd48920177 Mon Sep 17 00:00:00 2001
From: Brad Bondurant <brad.bondurant@duke.edu>
Date: Wed, 16 Nov 2022 09:08:21 -0500
Subject: [PATCH] [nfc]zynq_us/slcr: rename pll regs

---
 libboard_zynq_us/src/slcr/crf_apb.rs | 46 ++++++++++++++--------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/libboard_zynq_us/src/slcr/crf_apb.rs b/libboard_zynq_us/src/slcr/crf_apb.rs
index a2ed421..c20ff5f 100644
--- a/libboard_zynq_us/src/slcr/crf_apb.rs
+++ b/libboard_zynq_us/src/slcr/crf_apb.rs
@@ -15,19 +15,19 @@ pub struct RegisterBlock {
     pub ir_enable: WO<u32>,
     pub ir_disable: WO<u32>,
     pub crf_wprot: RW<u32>,
-    pub apll_ctrl: PllCtrl,
-    pub apll_cfg: PllCfg,
-    pub apll_frac_cfg: PllFracCfg,
-    pub dpll_ctrl: PllCtrl,
-    pub dpll_cfg: PllCfg,
-    pub dpll_frac_cfg: PllFracCfg,
-    pub vpll_ctr: PllCtrl,
-    pub vpll_cfg: PllCfg,
-    pub vpll_frac_cfg: PllFracCfg,
+    pub apu_pll_ctrl: PllCtrl,
+    pub apu_pll_cfg: PllCfg,
+    pub apu_pll_frac_cfg: PllFracCfg,
+    pub ddr_pll_ctrl: PllCtrl,
+    pub ddr_pll_cfg: PllCfg,
+    pub ddr_pll_frac_cfg: PllFracCfg,
+    pub video_pll_ctr: PllCtrl,
+    pub video_pll_cfg: PllCfg,
+    pub video_pll_frac_cfg: PllFracCfg,
     pub pll_status: PllStatus,
-    pub apll_to_lpd_ctrl: PllToLpdCtrl,
-    pub dpll_to_lpd_ctrl: PllToLpdCtrl,
-    pub vpll_to_lpd_ctrl: PllToLpdCtrl,
+    pub apu_pll_to_lpd_ctrl: PllToLpdCtrl,
+    pub ddr_pll_to_lpd_ctrl: PllToLpdCtrl,
+    pub video_pll_to_lpd_ctrl: PllToLpdCtrl,
     reserved1: [u32; 3],
     pub apu_clk_ctrl: ApuClkCtrl,
     pub dbg_trace_clk_ctrl: RW<u32>,
@@ -76,12 +76,12 @@ register_bit!(pll_frac_cfg, enabled, 31);
 register_bits!(pll_frac_cfg, data, u16, 0, 15);
 
 register!(pll_status, PllStatus, RO, u32);
-register_bit!(pll_status, vpll_stable, 5);
-register_bit!(pll_status, dpll_stable, 4);
-register_bit!(pll_status, apll_stable, 3);
-register_bit!(pll_status, vpll_lock, 2);
-register_bit!(pll_status, dpll_lock, 1);
-register_bit!(pll_status, apll_lock, 0);
+register_bit!(pll_status, video_pll_stable, 5);
+register_bit!(pll_status, ddr_pll_stable, 4);
+register_bit!(pll_status, apu_pll_stable, 3);
+register_bit!(pll_status, video_pll_lock, 2);
+register_bit!(pll_status, ddr_pll_lock, 1);
+register_bit!(pll_status, apu_pll_lock, 0);
 
 register!(pll_to_lpd_ctrl, PllToLpdCtrl, RW, u32);
 register_bits!(pll_to_lpd_ctrl, divisor0, u8, 8, 13);
@@ -90,13 +90,13 @@ register!(apu_clk_ctrl, ApuClkCtrl, RW, u32);
 register_bit!(apu_clk_ctrl, clkact_half, 25);
 register_bit!(apu_clk_ctrl, clkact_full, 24);
 register_bits!(apu_clk_ctrl, divisor0, u8, 8, 13);
-// 000: APLL
-// 010: DPLL
-// 011: VPLL
+// 000: APU PLL
+// 010: DDR PLL
+// 011: Video PLL
 register_bits!(apu_clk_ctrl, srcsel, u8, 0, 2);
 
 register!(ddr_clk_ctrl, DdrClkCtrl, RW, u32);
 register_bits!(ddr_clk_ctrl, divisor0, u8, 8, 13);
-// 000: DPLL
-// 001: VPLL
+// 000: DDR PLL
+// 001: Video PLL
 register_bits!(ddr_clk_ctrl, srcsel, u8, 0, 2);