From 0f2376410f82b75bb376b441e139c8f86012139f Mon Sep 17 00:00:00 2001 From: Brad Bondurant Date: Thu, 17 Nov 2022 15:44:11 -0500 Subject: [PATCH] zynq_us/slcr: add type enums for clksel fields --- libboard_zynq_us/src/slcr/crf_apb.rs | 15 +++--- libboard_zynq_us/src/slcr/crl_apb.rs | 79 +++++++++++++++++----------- 2 files changed, 56 insertions(+), 38 deletions(-) diff --git a/libboard_zynq_us/src/slcr/crf_apb.rs b/libboard_zynq_us/src/slcr/crf_apb.rs index 3a2388a..948f943 100644 --- a/libboard_zynq_us/src/slcr/crf_apb.rs +++ b/libboard_zynq_us/src/slcr/crf_apb.rs @@ -3,12 +3,18 @@ use volatile_register::{RO, RW, WO}; use libregister::{ register, register_at, - register_bit, register_bits, + register_bit, register_bits, register_bits_typed, RegisterW, }; use super::common::{SlcrRegisterBlock, WProt, PllCfg, PllCtrl, PllFracCfg}; +#[repr(u8)] +pub enum ApuClkSource { + ApuPll = 0b00, + DdrPll = 0b10, + VideoPll = 0b11, +} #[repr(C)] pub struct RegisterBlock { // CRF_APB @@ -24,7 +30,7 @@ pub struct RegisterBlock { pub ddr_pll_ctrl: PllCtrl, pub ddr_pll_cfg: PllCfg, pub ddr_pll_frac_cfg: PllFracCfg, - pub video_pll_ctr: PllCtrl, + pub video_pll_ctrl: PllCtrl, pub video_pll_cfg: PllCfg, pub video_pll_frac_cfg: PllFracCfg, pub pll_status: PllStatus, @@ -85,10 +91,7 @@ register!(apu_clk_ctrl, ApuClkCtrl, RW, u32); register_bit!(apu_clk_ctrl, clkact_half, 25); register_bit!(apu_clk_ctrl, clkact_full, 24); register_bits!(apu_clk_ctrl, divisor0, u8, 8, 13); -// 000: APU PLL -// 010: DDR PLL -// 011: Video PLL -register_bits!(apu_clk_ctrl, srcsel, u8, 0, 2); +register_bits_typed!(apu_clk_ctrl, srcsel, u8, ApuClkSource, 0, 2); register!(ddr_clk_ctrl, DdrClkCtrl, RW, u32); register_bits!(ddr_clk_ctrl, divisor0, u8, 8, 13); diff --git a/libboard_zynq_us/src/slcr/crl_apb.rs b/libboard_zynq_us/src/slcr/crl_apb.rs index 07a490e..264022a 100644 --- a/libboard_zynq_us/src/slcr/crl_apb.rs +++ b/libboard_zynq_us/src/slcr/crl_apb.rs @@ -3,11 +3,27 @@ use volatile_register::{RO, RW, WO}; use libregister::{ register, register_at, - register_bit, register_bits, + register_bit, register_bits, register_bits_typed, }; use super::common::{SlcrRegisterBlock, WProt, PllCfg, PllCtrl, PllFracCfg}; +/// Clock source selection for IO-type devices +#[repr(u8)] +pub enum IoClkSource { + IoPll = 0b00, + RpuPll = 0b10, + DdrPllToLpd = 0b11, +} + +/// Clock source selection for RPU and related (e.g. LPD interconnect) devices +#[repr(u8)] +pub enum RpuClkSource { + RpuPll = 0b00, + IoPll = 0b10, + DdrPllToLpd = 0b11, +} + #[repr(C)] pub struct RegisterBlock { pub err_ctrl: RW, @@ -26,8 +42,8 @@ pub struct RegisterBlock { pub rpu_pll_frac_cfg: PllFracCfg, reserved3: [u32; 1], pub pll_status: PllStatus, - pub io_pll_to_lpd_ctrl: PllToFpdCtrl, - pub rpu_pll_to_lpd_ctrl: PllToFpdCtrl, + pub io_pll_to_fpd_ctrl: PllToFpdCtrl, + pub rpu_pll_to_fpd_ctrl: PllToFpdCtrl, pub usb3_clk_ctrl: UsbClkCtrl, pub gem0_clk_ctrl: GemClkCtrl, pub gem1_clk_ctrl: GemClkCtrl, @@ -48,7 +64,7 @@ pub struct RegisterBlock { pub rpu_clk_ctrl: RpuClkCtrl, reserved5: [u32; 2], pub iou_switch_clk_ctrl: IouSwitchClkCtrl, - pub csu_pll_ctrl: CsuPllCtrl, + pub csu_clk_ctrl: CsuPllCtrl, pub pcap_clk_ctrl: PcapClkCtrl, pub lpd_switch_clk_ctrl: LpdSwitchClkCtrl, pub lpd_lsbus_clk_ctrl: LpdLsbusClkCtrl, @@ -166,66 +182,65 @@ register_bit!(gem_clk_ctrl, rx_clkact, 26); register_bit!(gem_clk_ctrl, clkact, 25); register_bits!(gem_clk_ctrl, divisor1, u8, 16, 21); register_bits!(gem_clk_ctrl, divisor0, u8, 8, 13); -// 000: IOPLL -// 010: RPLL -// 011: DPLL_CLK_TO_LPD -register_bits!(gem_clk_ctrl, srcsel, u8, 0, 2); +register_bits_typed!(gem_clk_ctrl, srcsel, u8, IoClkSource, 0, 2); register!(usb_clk_ctrl, UsbClkCtrl, RW, u32); register_bit!(usb_clk_ctrl, clkact, 25); register_bits!(usb_clk_ctrl, divisor1, u8, 16, 21); register_bits!(usb_clk_ctrl, divisor0, u8, 8, 13); -register_bits!(usb_clk_ctrl, srcsel, u8, 0, 2); +register_bits_typed!(usb_clk_ctrl, srcsel, u8, IoClkSource, 0, 2); macro_rules! dual_div_clk_reg { - ($mod_name: ident, $struct_name: ident) => { + ($mod_name: ident, $struct_name: ident, $srcsel_type: ident) => { register!($mod_name, $struct_name, RW, u32); register_bit!($mod_name, clkact, 24); register_bits!($mod_name, divisor1, u8, 16, 21); register_bits!($mod_name, divisor0, u8, 8, 13); - register_bits!($mod_name, srcsel, u8, 0, 2); + register_bits_typed!($mod_name, srcsel, u8, $srcsel_type, 0, 2); }; } -dual_div_clk_reg!(qspi_clk_ctrl, QSpiClkCtrl); -dual_div_clk_reg!(sdio_clk_ctrl, SdioClkCtrl); -dual_div_clk_reg!(uart_clk_ctrl, UartClkCtrl); -dual_div_clk_reg!(spi_clk_ctrl, SpiClkCtrl); -dual_div_clk_reg!(can_clk_ctrl, CanClkCtrl); -dual_div_clk_reg!(nand_clk_ctrl, NandClkCtrl); -dual_div_clk_reg!(pl_clk_ctrl, PlClkCtrl); -dual_div_clk_reg!(gem_tsu_clk_ctrl, GemTsuClkCtrl); -dual_div_clk_reg!(ps_sysmon_clk_ctrl, PsSysmonClkCtrl); -dual_div_clk_reg!(i2c_clk_ctrl, I2cClkCtrl); +dual_div_clk_reg!(qspi_clk_ctrl, QSpiClkCtrl, IoClkSource); +dual_div_clk_reg!(sdio_clk_ctrl, SdioClkCtrl, IoClkSource); +dual_div_clk_reg!(uart_clk_ctrl, UartClkCtrl, IoClkSource); +dual_div_clk_reg!(spi_clk_ctrl, SpiClkCtrl, IoClkSource); +dual_div_clk_reg!(can_clk_ctrl, CanClkCtrl, IoClkSource); +dual_div_clk_reg!(nand_clk_ctrl, NandClkCtrl, IoClkSource); +dual_div_clk_reg!(pl_clk_ctrl, PlClkCtrl, IoClkSource); +dual_div_clk_reg!(gem_tsu_clk_ctrl, GemTsuClkCtrl, IoClkSource); +dual_div_clk_reg!(ps_sysmon_clk_ctrl, PsSysmonClkCtrl, RpuClkSource); +dual_div_clk_reg!(i2c_clk_ctrl, I2cClkCtrl, IoClkSource); register!(rpu_clk_ctrl, RpuClkCtrl, RW, u32); register_bit!(rpu_clk_ctrl, clkact_core, 25); register_bit!(rpu_clk_ctrl, clkact, 24); register_bits!(rpu_clk_ctrl, divisor0, u8, 8, 13); -register_bits!(rpu_clk_ctrl, srcsel, u8, 0, 2); +register_bits_typed!(rpu_clk_ctrl, srcsel, u8, RpuClkSource, 0, 2); macro_rules! single_div_clk_reg { - ($mod_name: ident, $struct_name: ident) => { + // default to RpuClkSource + ($mod_name: ident, $struct_name: ident, $srcsel_type: ident) => { register!($mod_name, $struct_name, RW, u32); register_bit!($mod_name, clkact, 24); register_bits!($mod_name, divisor1, u8, 16, 21); register_bits!($mod_name, divisor0, u8, 8, 13); - register_bits!($mod_name, srcsel, u8, 0, 2); + register_bits_typed!($mod_name, srcsel, u8, $srcsel_type, 0, 2); }; } -single_div_clk_reg!(iou_switch_clk_ctrl, IouSwitchClkCtrl); -single_div_clk_reg!(csu_pll_ctrl, CsuPllCtrl); -single_div_clk_reg!(pcap_clk_ctrl, PcapClkCtrl); -single_div_clk_reg!(lpd_switch_clk_ctrl, LpdSwitchClkCtrl); -single_div_clk_reg!(lpd_lsbus_clk_ctrl, LpdLsbusClkCtrl); -single_div_clk_reg!(dbg_lpd_clk_ctrl, DbgLpdClkCtrl); -single_div_clk_reg!(lpd_dma_clk_ctrl, LpdDmaClkCtrl); -single_div_clk_reg!(timestamp_clk_ctrl, TimestampClkCtrl); +single_div_clk_reg!(iou_switch_clk_ctrl, IouSwitchClkCtrl, RpuClkSource); +single_div_clk_reg!(csu_clk_ctrl, CsuPllCtrl, IoClkSource); +single_div_clk_reg!(pcap_clk_ctrl, PcapClkCtrl, IoClkSource); +single_div_clk_reg!(lpd_switch_clk_ctrl, LpdSwitchClkCtrl, RpuClkSource); +single_div_clk_reg!(lpd_lsbus_clk_ctrl, LpdLsbusClkCtrl, RpuClkSource); +single_div_clk_reg!(dbg_lpd_clk_ctrl, DbgLpdClkCtrl, RpuClkSource); +single_div_clk_reg!(lpd_dma_clk_ctrl, LpdDmaClkCtrl, RpuClkSource); +// todo: timestamp clk can also run directly from PS_REF_CLK (0b1xx) +single_div_clk_reg!(timestamp_clk_ctrl, TimestampClkCtrl, IoClkSource); register!(pl_thr_ctrl, PlThrCtrl, RW, u32);