#
# ZC706 (master device)
# -----------------------------------------------------------------------------

# NIST_QC2
core_addr = "172.20.20.2"

# sysclk: dds clock frequency - usually 2.4 GHz for magtrap
# sysclk is divided by 24 to give refclk (100 MHz) to clock the FPGA
# each period of this coarse clock is subdivided
# into 8 to give ref_period (= 1 machine unit)
sysclk = 2.4e9
f_rtio = sysclk / 24
ref_period = 1.0 / (8 * f_rtio)

device_db = {
    "core": {
        "type": "local",
        "module": "artiq.coredevice.core",
        "class": "Core",
        "arguments": {
            "host": core_addr,
            "ref_period": ref_period,
            "ref_multiplier": 8,
            "target": "cortexa9"
        }
    },
    "core_log": {
        "type": "controller",
        "host": "::1",
        "port": 1068,
        "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
    },
    "core_moninj": {
        "type": "controller",
        "host": "::1",
        "port_proxy": 1383,
        "port": 1384,
        "command": "aqctl_moninj_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} " + core_addr
    },
    "core_cache": {
        "type": "local",
        "module": "artiq.coredevice.cache",
        "class": "CoreCache"
    },
    "core_dma": {
        "type": "local",
        "module": "artiq.coredevice.dma",
        "class": "CoreDMA"
    },
    "pca": {
        "type": "local",
        "module": "artiq.coredevice.i2c",
        "class": "I2CSwitch",
    },
    "tca": {
        "type": "local",
        "module": "artiq.coredevice.i2c",
        "class": "TCA6424A",
    },
    "led": {
        "type": "local",
        "module": "artiq.coredevice.ttl",
        "class": "TTLOut",
        "arguments": {
            "channel": 41
        }
    },
}

# TTLs on QC2 backplane
for i in range(40):
    device_db["ttl" + str(i)] = {
        "type": "local",
        "module": "artiq.coredevice.ttl",
        "class": "TTLInOut",
        "arguments": {
            "channel": i
        }
    }

# TTL clocks
for i in range(2):
    device_db["ttl_clk" + str(i)] = {
        "type": "local",
        "module": "artiq.coredevice.ttl",
        "class": "TTLClockGen",
        "arguments": {
            "channel": 44 + i
        }
    }

# SPI buses
for i in range(4):
    device_db["spi" + str(i)] = {
        "type": "local",
        "module": "artiq.coredevice.spi2",
        "class": "SPIMaster",
        "arguments": {
            "channel": 46 + i
        }
    }

# DDSes
for i in range(12):
    # redundant since we don't have >12 DDS, but
    # leave it in anyway
    backplane = i // 12
    dds = i % 12
    device_db["ad9914dds" + str(i)] = {
        "type": "local",
        "module": "artiq.coredevice.ad9914",
        "class": "AD9914",
        "arguments": {
            "sysclk": sysclk,
            "bus_channel": 50 + backplane,
            "channel": dds
        }
    }


#
# Kasli v1.1 (calcium satellite)
# -----------------------------------------------------------------------------

# TTLs
for i in range(16):
    device_db["kasli_ttl" + str(i)] = {
        "type": "local",
        "module": "artiq.coredevice.ttl",
        "class": "TTLInOut",
        "arguments": {
            "channel": 0x010000 + i
        }
    }

# SPI buses
for i in range(4):
    device_db["kasli_spi" + str(i)] = {
        "type": "local",
        "module": "artiq.coredevice.spi2",
        "class": "SPIMaster",
        "arguments": {
            "channel": 0x010010 + i
        }
    }