Open On-Chip Debugger 0.11.0
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
User : 13 4 options.c:63 configuration_output_handler(): debug_level: 3
User : 14 4 options.c:63 configuration_output_handler(): 
Debug: 15 4 options.c:244 add_default_dirs(): bindir=/nix/store/qfpin5wnkj84zkd39x565id321vhim0v-openocd-0.11.0/bin
Debug: 16 4 options.c:245 add_default_dirs(): pkgdatadir=/nix/store/qfpin5wnkj84zkd39x565id321vhim0v-openocd-0.11.0/share/openocd
Debug: 17 4 options.c:246 add_default_dirs(): exepath=/nix/store/qfpin5wnkj84zkd39x565id321vhim0v-openocd-0.11.0/bin
Debug: 18 4 options.c:247 add_default_dirs(): bin2data=../share/openocd
Debug: 19 4 configuration.c:42 add_script_search_dir(): adding /home/jfoley/.config/openocd
Debug: 20 5 configuration.c:42 add_script_search_dir(): adding /home/jfoley/.openocd
Debug: 21 5 configuration.c:42 add_script_search_dir(): adding /nix/store/qfpin5wnkj84zkd39x565id321vhim0v-openocd-0.11.0/bin/../share/openocd/site
Debug: 22 5 configuration.c:42 add_script_search_dir(): adding /nix/store/qfpin5wnkj84zkd39x565id321vhim0v-openocd-0.11.0/bin/../share/openocd/scripts
Debug: 23 5 configuration.c:97 find_file(): found kasli_soc.cfg
Debug: 24 5 command.c:146 script_debug(): command - adapter driver ftdi
Debug: 26 5 command.c:146 script_debug(): command - ftdi_device_desc Quad RS232-HS
Debug: 28 5 command.c:146 script_debug(): command - ftdi_vid_pid 0x0403 0x6011
Debug: 30 5 command.c:146 script_debug(): command - ftdi_channel 0
Debug: 32 5 command.c:146 script_debug(): command - ftdi_layout_init 0x0098 0x008b
Debug: 34 5 command.c:146 script_debug(): command - transport select jtag
Debug: 35 6 command.c:146 script_debug(): command - adapter speed 1000
Debug: 37 6 core.c:1822 jtag_config_khz(): handle jtag khz
Debug: 38 6 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 39 6 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 40 6 command.c:146 script_debug(): command - jtag newtap zynq tap -irlen 6 -ircapture 0x001 -irmask 0x003 -expected-id 0x1372c093
Debug: 41 6 tcl.c:571 jim_newtap_cmd(): Creating New Tap, Chip: zynq, Tap: tap, Dotted: zynq.tap, 8 params
Debug: 42 6 tcl.c:596 jim_newtap_cmd(): Processing option: -irlen
Debug: 43 6 tcl.c:596 jim_newtap_cmd(): Processing option: -ircapture
Debug: 44 6 tcl.c:596 jim_newtap_cmd(): Processing option: -irmask
Debug: 45 6 tcl.c:596 jim_newtap_cmd(): Processing option: -expected-id
Debug: 46 6 core.c:1484 jtag_tap_init(): Created Tap: zynq.tap @ abs position 0, irlen 6, capture: 0x1 mask: 0x3
Debug: 47 6 command.c:146 script_debug(): command - jtag newtap zynq dap -irlen 4 -ircapture 0x01 -irmask 0x03 -expected-id 0x4ba00477
Debug: 48 6 tcl.c:571 jim_newtap_cmd(): Creating New Tap, Chip: zynq, Tap: dap, Dotted: zynq.dap, 8 params
Debug: 49 6 tcl.c:596 jim_newtap_cmd(): Processing option: -irlen
Debug: 50 6 tcl.c:596 jim_newtap_cmd(): Processing option: -ircapture
Debug: 51 6 tcl.c:596 jim_newtap_cmd(): Processing option: -irmask
Debug: 52 7 tcl.c:596 jim_newtap_cmd(): Processing option: -expected-id
Debug: 53 7 core.c:1484 jtag_tap_init(): Created Tap: zynq.dap @ abs position 1, irlen 4, capture: 0x1 mask: 0x3
Debug: 54 7 command.c:146 script_debug(): command - dap create zynq.dap -chain-position zynq.dap
Debug: 55 7 command.c:146 script_debug(): command - target create zynq.cpu.0 cortex_a -coreid 0 -endian little -dap zynq.dap -dbgbase 0x80090000
Debug: 56 7 command.c:146 script_debug(): command - echo Zynq CPU1.
User : 58 7 command.c:769 jim_echo(): Zynq CPU1.
Debug: 59 8 command.c:146 script_debug(): command - target create zynq.cpu.1 cortex_a -coreid 1 -endian little -dap zynq.dap -dbgbase 0x80092000
Debug: 60 8 command.c:375 register_command(): command 'arm' is already registered in '<global>' context
Debug: 61 8 command.c:375 register_command(): command 'reg' is already registered in 'arm' context
Debug: 62 8 command.c:375 register_command(): command 'core_state' is already registered in 'arm' context
Debug: 63 8 command.c:375 register_command(): command 'disassemble' is already registered in 'arm' context
Debug: 64 8 command.c:375 register_command(): command 'mcr' is already registered in 'arm' context
Debug: 65 8 command.c:375 register_command(): command 'mrc' is already registered in 'arm' context
Debug: 66 8 command.c:375 register_command(): command 'semihosting' is already registered in 'arm' context
Debug: 67 8 command.c:375 register_command(): command 'semihosting_cmdline' is already registered in 'arm' context
Debug: 68 8 command.c:375 register_command(): command 'semihosting_fileio' is already registered in 'arm' context
Debug: 69 8 command.c:375 register_command(): command 'semihosting_resexit' is already registered in 'arm' context
Debug: 70 8 command.c:375 register_command(): command 'cache_config' is already registered in '<global>' context
Debug: 71 8 command.c:375 register_command(): command 'l2x' is already registered in 'cache_config' context
Debug: 72 8 command.c:375 register_command(): command 'cache' is already registered in '<global>' context
Debug: 73 8 command.c:375 register_command(): command 'auto' is already registered in 'cache' context
Debug: 74 8 command.c:375 register_command(): command 'l1' is already registered in 'cache' context
Debug: 75 8 command.c:375 register_command(): command 'info' is already registered in 'l1' context
Debug: 76 8 command.c:375 register_command(): command 'd' is already registered in 'l1' context
Debug: 77 8 command.c:375 register_command(): command 'flush_all' is already registered in 'd' context
Debug: 78 9 command.c:375 register_command(): command 'inval' is already registered in 'd' context
Debug: 79 9 command.c:375 register_command(): command 'clean' is already registered in 'd' context
Debug: 80 9 command.c:375 register_command(): command 'i' is already registered in 'l1' context
Debug: 81 9 command.c:375 register_command(): command 'inval_all' is already registered in 'i' context
Debug: 82 9 command.c:375 register_command(): command 'inval' is already registered in 'i' context
Debug: 83 9 command.c:375 register_command(): command 'l2x' is already registered in 'cache' context
Debug: 84 9 command.c:375 register_command(): command 'conf' is already registered in 'l2x' context
Debug: 85 9 command.c:375 register_command(): command 'info' is already registered in 'l2x' context
Debug: 86 9 command.c:375 register_command(): command 'flush_all' is already registered in 'l2x' context
Debug: 87 9 command.c:375 register_command(): command 'flush' is already registered in 'l2x' context
Debug: 88 9 command.c:375 register_command(): command 'inval' is already registered in 'l2x' context
Debug: 89 9 command.c:375 register_command(): command 'clean' is already registered in 'l2x' context
Debug: 90 9 command.c:375 register_command(): command 'cortex_a' is already registered in '<global>' context
Debug: 91 9 command.c:375 register_command(): command 'cache_info' is already registered in 'cortex_a' context
Debug: 92 9 command.c:375 register_command(): command 'dbginit' is already registered in 'cortex_a' context
Debug: 93 9 command.c:375 register_command(): command 'maskisr' is already registered in 'cortex_a' context
Debug: 94 9 command.c:375 register_command(): command 'dacrfixup' is already registered in 'cortex_a' context
Debug: 95 9 command.c:375 register_command(): command 'mmu' is already registered in 'cortex_a' context
Debug: 96 9 command.c:375 register_command(): command 'dump' is already registered in 'mmu' context
Debug: 97 9 command.c:375 register_command(): command 'smp' is already registered in 'cortex_a' context
Debug: 98 9 command.c:375 register_command(): command 'smp_on' is already registered in 'cortex_a' context
Debug: 99 9 command.c:375 register_command(): command 'smp_off' is already registered in 'cortex_a' context
Debug: 100 9 command.c:375 register_command(): command 'smp_gdb' is already registered in 'cortex_a' context
Debug: 101 10 command.c:146 script_debug(): command - target smp zynq.cpu.0 zynq.cpu.1
Debug: 102 10 target.c:5935 jim_target_smp(): 3
Debug: 103 10 target.c:5945 jim_target_smp(): zynq.cpu.0 
Debug: 104 10 target.c:5945 jim_target_smp(): zynq.cpu.1 
Debug: 105 10 command.c:146 script_debug(): command - ftdi_layout_signal nSRST -oe 0x0004
Debug: 107 10 command.c:146 script_debug(): command - reset_config srst_only srst_open_drain
Debug: 109 10 command.c:146 script_debug(): command - adapter srst pulse_width 250
Debug: 111 10 command.c:146 script_debug(): command - adapter srst delay 400
Debug: 113 10 command.c:146 script_debug(): command - pld device virtex2 zynq.tap 1
Debug: 115 10 command.c:146 script_debug(): command - init
Debug: 117 10 command.c:146 script_debug(): command - target init
Debug: 119 11 command.c:146 script_debug(): command - target names
Debug: 120 11 command.c:146 script_debug(): command - zynq.cpu.0 cget -event gdb-flash-erase-start
Debug: 121 11 command.c:146 script_debug(): command - zynq.cpu.0 configure -event gdb-flash-erase-start reset init
Debug: 122 11 command.c:146 script_debug(): command - zynq.cpu.0 cget -event gdb-flash-write-end
Debug: 123 11 command.c:146 script_debug(): command - zynq.cpu.0 configure -event gdb-flash-write-end reset halt
Debug: 124 11 command.c:146 script_debug(): command - zynq.cpu.0 cget -event gdb-attach
Debug: 125 11 command.c:146 script_debug(): command - zynq.cpu.0 configure -event gdb-attach halt 1000
Debug: 126 11 command.c:146 script_debug(): command - zynq.cpu.1 cget -event gdb-flash-erase-start
Debug: 127 11 command.c:146 script_debug(): command - zynq.cpu.1 configure -event gdb-flash-erase-start reset init
Debug: 128 11 command.c:146 script_debug(): command - zynq.cpu.1 cget -event gdb-flash-write-end
Debug: 129 11 command.c:146 script_debug(): command - zynq.cpu.1 configure -event gdb-flash-write-end reset halt
Debug: 130 11 command.c:146 script_debug(): command - zynq.cpu.1 cget -event gdb-attach
Debug: 131 11 command.c:146 script_debug(): command - zynq.cpu.1 configure -event gdb-attach halt 1000
Debug: 132 11 target.c:1639 handle_target_init_command(): Initializing targets...
Debug: 133 11 semihosting_common.c:99 semihosting_common_init():  
Debug: 134 11 semihosting_common.c:99 semihosting_common_init():  
Debug: 135 12 ftdi.c:650 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Debug: 136 61 mpsse.c:422 mpsse_purge(): -
Debug: 137 62 mpsse.c:703 mpsse_loopback_config(): off
Debug: 138 62 mpsse.c:748 mpsse_set_frequency(): target 1000000 Hz
Debug: 139 62 mpsse.c:740 mpsse_rtck_config(): off
Debug: 140 62 mpsse.c:729 mpsse_divide_by_5_config(): off
Debug: 141 62 mpsse.c:709 mpsse_set_divisor(): 29
Debug: 142 62 mpsse.c:772 mpsse_set_frequency(): actually 1000000 Hz
Debug: 143 63 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 144 63 core.c:1789 adapter_khz_to_speed(): have interface set up
Debug: 145 63 mpsse.c:748 mpsse_set_frequency(): target 1000000 Hz
Debug: 146 63 mpsse.c:740 mpsse_rtck_config(): off
Debug: 147 63 mpsse.c:729 mpsse_divide_by_5_config(): off
Debug: 148 63 mpsse.c:709 mpsse_set_divisor(): 29
Debug: 149 63 mpsse.c:772 mpsse_set_frequency(): actually 1000000 Hz
Debug: 150 63 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 151 63 core.c:1789 adapter_khz_to_speed(): have interface set up
Info : 152 63 core.c:1565 adapter_init(): clock speed 1000 kHz
Debug: 153 63 openocd.c:143 handle_init_command(): Debug Adapter init complete
Debug: 154 63 command.c:146 script_debug(): command - transport init
Debug: 156 63 transport.c:229 handle_transport_init(): handle_transport_init
Debug: 157 64 core.c:830 jtag_add_reset(): SRST line released
Debug: 158 64 core.c:855 jtag_add_reset(): TRST line released
Debug: 159 64 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 160 483 command.c:146 script_debug(): command - jtag arp_init
Debug: 161 483 core.c:1578 jtag_init_inner(): Init JTAG chain
Debug: 162 484 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 163 484 core.c:1243 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 164 484 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 165 485 core.c:1142 jtag_examine_chain_display(): JTAG tap: zynq.tap tap/device found: 0x1372c093 (mfg: 0x049 (Xilinx), part: 0x372c, ver: 0x1)
Info : 166 485 core.c:1142 jtag_examine_chain_display(): JTAG tap: zynq.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4)
Debug: 167 485 core.c:1374 jtag_validate_ircapture(): IR capture validation scan
Debug: 168 486 core.c:1431 jtag_validate_ircapture(): zynq.tap: IR capture 0x11
Debug: 169 486 core.c:1431 jtag_validate_ircapture(): zynq.dap: IR capture 0x01
Debug: 170 486 command.c:146 script_debug(): command - dap init
Debug: 172 486 arm_dap.c:106 dap_init_all(): Initializing all DAPs ...
Debug: 173 486 arm_adi_v5.c:653 dap_dp_init(): zynq.dap
Debug: 174 486 arm_adi_v5.c:685 dap_dp_init(): DAP: wait CDBGPWRUPACK
Debug: 175 486 arm_adi_v5.h:506 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
Debug: 176 487 arm_adi_v5.c:693 dap_dp_init(): DAP: wait CSYSPWRUPACK
Debug: 177 487 arm_adi_v5.h:506 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
Debug: 178 488 openocd.c:160 handle_init_command(): Examining targets...
Debug: 179 488 target.c:1825 target_call_event_callbacks(): target event 19 (examine-start) for core zynq.cpu.0
Debug: 180 490 arm_adi_v5.c:898 dap_find_ap(): Found APB-AP at AP index: 1 (IDR=0x24770002)
Debug: 181 491 arm_adi_v5.c:792 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 182 491 arm_adi_v5.c:803 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 183 493 cortex_a.c:2742 cortex_a_examine_first(): didr = 0x35137030
Debug: 184 493 cortex_a.c:2743 cortex_a_examine_first(): cpuid = 0x413fc090
Debug: 185 494 cortex_a.c:2752 cortex_a_examine_first(): target->coreid 0 DBGPRSR  0x1
Debug: 186 495 cortex_a.c:2768 cortex_a_examine_first(): target->coreid 0 DBGOSLSR 0x0
Debug: 187 496 cortex_a.c:2799 cortex_a_examine_first(): target->coreid 0 has security extensions
Info : 188 496 arm_dpm.c:1109 arm_dpm_setup(): zynq.cpu.0: hardware has 6 breakpoints, 4 watchpoints
Debug: 189 496 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 80090140
Debug: 190 497 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 80090144
Debug: 191 498 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 80090148
Debug: 192 498 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 8009014c
Debug: 193 499 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 80090150
Debug: 194 499 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 80090154
Debug: 195 500 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 800901c0
Debug: 197 501 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 800901c4
Debug: 198 501 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 800901c8
Debug: 199 502 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 800901cc
Debug: 200 502 cortex_a.c:2838 cortex_a_examine_first(): Configured 6 hw breakpoints
Debug: 201 505 target.c:1825 target_call_event_callbacks(): target event 21 (examine-end) for core zynq.cpu.0
Debug: 202 505 target.c:1825 target_call_event_callbacks(): target event 19 (examine-start) for core zynq.cpu.1
Debug: 203 507 arm_adi_v5.c:898 dap_find_ap(): Found APB-AP at AP index: 1 (IDR=0x24770002)
Debug: 204 507 arm_adi_v5.c:792 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 205 507 arm_adi_v5.c:803 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 206 509 cortex_a.c:2742 cortex_a_examine_first(): didr = 0x35137030
Debug: 207 509 cortex_a.c:2743 cortex_a_examine_first(): cpuid = 0x413fc090
Debug: 208 510 cortex_a.c:2752 cortex_a_examine_first(): target->coreid 1 DBGPRSR  0x1
Debug: 209 511 cortex_a.c:2768 cortex_a_examine_first(): target->coreid 1 DBGOSLSR 0x0
Debug: 210 511 cortex_a.c:2799 cortex_a_examine_first(): target->coreid 1 has security extensions
Info : 211 511 arm_dpm.c:1109 arm_dpm_setup(): zynq.cpu.1: hardware has 6 breakpoints, 4 watchpoints
Debug: 212 511 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 80092140
Debug: 213 512 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 80092144
Debug: 214 513 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 80092148
Debug: 215 513 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 8009214c
Debug: 216 514 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 80092150
Debug: 217 515 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 80092154
Debug: 218 515 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 800921c0
Debug: 219 516 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 800921c4
Debug: 220 517 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 800921c8
Debug: 221 517 cortex_a.c:591 cortex_a_bpwp_disable(): A: bpwp disable, cr 800921cc
Debug: 222 518 cortex_a.c:2838 cortex_a_examine_first(): Configured 6 hw breakpoints
Debug: 223 521 cortex_a.c:730 cortex_a_poll(): Target halted
Debug: 224 521 cortex_a.c:1000 cortex_a_debug_entry(): dscr = 0x03086003
Debug: 225 522 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 226 524 arm_dpm.c:234 arm_dpm_read_reg(): READ: r0, 60000113
Debug: 227 524 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee001e15
Debug: 228 525 arm_dpm.c:234 arm_dpm_read_reg(): READ: r1, 0028c0b8
Debug: 229 525 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xe10f0000
Debug: 230 526 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 231 527 armv4_5.c:496 arm_set_cpsr(): set CPSR 0x60000113: Supervisor mode, ARM state
Debug: 232 527 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee002e15
Debug: 233 529 arm_dpm.c:234 arm_dpm_read_reg(): READ: r2, 00000000
Debug: 234 529 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee003e15
Debug: 235 530 arm_dpm.c:234 arm_dpm_read_reg(): READ: r3, 0028c088
Debug: 236 530 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee004e15
Debug: 237 531 arm_dpm.c:234 arm_dpm_read_reg(): READ: r4, 0028c0d0
Debug: 238 531 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee005e15
Debug: 239 533 arm_dpm.c:234 arm_dpm_read_reg(): READ: r5, 11293e00
Debug: 240 533 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee006e15
Debug: 241 534 arm_dpm.c:234 arm_dpm_read_reg(): READ: r6, 00000000
Debug: 242 534 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee007e15
Debug: 243 535 arm_dpm.c:234 arm_dpm_read_reg(): READ: r7, 11293eb4
Debug: 244 535 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee008e15
Debug: 245 537 arm_dpm.c:234 arm_dpm_read_reg(): READ: r8, 11293e84
Debug: 246 537 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee009e15
Debug: 247 538 arm_dpm.c:234 arm_dpm_read_reg(): READ: r9, 11293ee0
Debug: 248 538 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee00ae15
Debug: 249 539 arm_dpm.c:234 arm_dpm_read_reg(): READ: r10, 0028c0bc
Debug: 250 539 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee00be15
Debug: 251 541 arm_dpm.c:234 arm_dpm_read_reg(): READ: r11, 11294008
Debug: 252 541 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee00ce15
Debug: 253 542 arm_dpm.c:234 arm_dpm_read_reg(): READ: r12, 0028c0d4
Debug: 254 542 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee00de15
Debug: 255 543 arm_dpm.c:234 arm_dpm_read_reg(): READ: sp_svc, 11293c68
Debug: 256 543 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee00ee15
Debug: 257 544 arm_dpm.c:234 arm_dpm_read_reg(): READ: lr_svc, 0017817c
Debug: 258 545 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xe1a0000f
Debug: 259 545 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 260 547 arm_dpm.c:234 arm_dpm_read_reg(): READ: pc, 0017b170
Debug: 261 547 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xe14f0000
Debug: 262 547 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 263 549 arm_dpm.c:234 arm_dpm_read_reg(): READ: spsr_svc, 00000000
Debug: 264 549 arm_dpm.c:64 dpm_mrc(): MRC p15, 0, r0, c1, c0, 0
Debug: 265 549 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee110f10
Debug: 266 550 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 267 551 cortex_a.c:1084 cortex_a_post_debug_entry(): cp15_control_reg: 08c5187d
Debug: 268 552 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee120f50
Debug: 269 553 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 270 554 armv7a.c:147 armv7a_read_ttbcr(): ttbcr 0
Debug: 271 554 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee120f10
Debug: 272 555 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 273 556 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee120f30
Debug: 274 557 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 275 559 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100f10
Debug: 276 560 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Info : 277 561 armv7a.c:114 armv7a_read_midr(): zynq.cpu.1 rev 0, partnum c09, arch f, variant 3, implementor 41
Debug: 278 561 armv7a.c:182 armv7a_read_ttbcr(): ttbr1 not used, ttbr0_mask ffffc000 ttbr1_mask ffffc000
Debug: 279 561 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100f30
Debug: 280 562 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 281 563 armv7a.c:402 armv7a_identify_cache(): ctr 83338003 ctr.iminline 32 ctr.dminline 32
Debug: 282 564 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee300f30
Debug: 283 564 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 284 566 armv7a.c:414 armv7a_identify_cache(): Number of cache levels to PoC 1
Debug: 285 566 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee500f10
Debug: 286 566 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 287 568 cortex_a.c:343 cortex_a_write_dcc(): write DCC 0x00000000
Debug: 288 568 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100e15
Debug: 289 569 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee400f10
Debug: 290 569 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee300f10
Debug: 291 570 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 292 571 armv7a.c:442 armv7a_identify_cache(): data/unified cache index 255 << 5, way 3 << 30
Debug: 293 571 armv7a.c:448 armv7a_identify_cache(): cacheline 32 bytes 32 KBytes asso 4 ways
Debug: 294 571 cortex_a.c:343 cortex_a_write_dcc(): write DCC 0x00000001
Debug: 295 571 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100e15
Debug: 296 572 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee400f10
Debug: 297 573 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee300f10
Debug: 298 574 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 299 575 armv7a.c:462 armv7a_identify_cache(): instruction cache index 255 << 5, way 3 << 30
Debug: 300 575 armv7a.c:468 armv7a_identify_cache(): cacheline 32 bytes 32 KBytes asso 4 ways
Debug: 301 576 cortex_a.c:343 cortex_a_write_dcc(): write DCC 0x00000001
Debug: 302 576 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100e15
Debug: 303 576 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee500f10
Debug: 304 578 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100fb0
Debug: 305 578 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 306 580 armv7a.c:312 armv7a_read_mpidr(): zynq.cpu.1: MPIDR 0x80000001
Info : 307 580 armv7a.c:318 armv7a_read_mpidr(): zynq.cpu.1: MPIDR level2 0, cluster 0, core 1, multi core, no SMT
Debug: 308 580 cortex_a.c:343 cortex_a_write_dcc(): write DCC 0x00000013
Debug: 309 580 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100e15
Debug: 310 581 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xe12ff000
Debug: 311 582 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee070f95
Debug: 312 583 arm_dpm.c:64 dpm_mrc(): MRC p15, 0, r0, c3, c0, 0
Debug: 313 583 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee130f10
Debug: 314 584 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 315 585 cortex_a.c:1111 cortex_a_post_debug_entry(): cp15_dacr_reg: ffffffff
Debug: 316 585 cortex_a.c:343 cortex_a_write_dcc(): write DCC 0x60000113
Debug: 317 585 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100e15
Debug: 318 586 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xe12ff000
Debug: 319 587 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee070f95
Debug: 320 588 target.c:1825 target_call_event_callbacks(): target event 0 (gdb-halt) for core zynq.cpu.1
Debug: 321 588 target.c:1825 target_call_event_callbacks(): target event 1 (halted) for core zynq.cpu.1
Debug: 322 588 target.c:1825 target_call_event_callbacks(): target event 21 (examine-end) for core zynq.cpu.1
Debug: 323 588 command.c:146 script_debug(): command - flash init
Debug: 325 590 tcl.c:1385 handle_flash_init_command(): Initializing flash devices...
Debug: 326 590 command.c:146 script_debug(): command - nand init
Debug: 328 591 tcl.c:498 handle_nand_init_command(): Initializing NAND devices...
Debug: 329 591 command.c:146 script_debug(): command - pld init
Debug: 331 593 pld.c:206 handle_pld_init_command(): Initializing PLDs...
Info : 332 593 gdb_server.c:3503 gdb_target_start(): starting gdb server for zynq.cpu.0 on 3333
Info : 333 593 server.c:311 add_service(): Listening on port 3333 for gdb connections
Debug: 334 593 command.c:146 script_debug(): command - irscan zynq.tap 0x0d
Debug: 336 595 command.c:146 script_debug(): command - irscan zynq.tap 0x0b
Debug: 338 597 command.c:146 script_debug(): command - runtest 60000
Debug: 340 658 command.c:146 script_debug(): command - runtest 2000
Debug: 342 664 command.c:146 script_debug(): command - irscan zynq.tap 0x3f
Debug: 344 669 command.c:146 script_debug(): command - runtest 2000
Debug: 346 672 command.c:146 script_debug(): command - reset halt
Debug: 348 676 target.c:1844 target_call_reset_callbacks(): target reset 2 (halt)
Debug: 349 676 target.c:1844 target_call_reset_callbacks(): target reset 2 (halt)
Debug: 350 677 command.c:146 script_debug(): command - target names
Debug: 351 677 command.c:146 script_debug(): command - zynq.cpu.0 invoke-event reset-start
Debug: 352 677 command.c:146 script_debug(): command - zynq.cpu.1 invoke-event reset-start
Debug: 353 677 command.c:146 script_debug(): command - transport select
Debug: 354 677 command.c:146 script_debug(): command - jtag arp_init-reset
Debug: 355 677 core.c:1694 jtag_init_reset(): Initializing with hard TRST+SRST reset
Debug: 356 677 core.c:826 jtag_add_reset(): SRST line asserted
Debug: 357 677 core.c:843 jtag_add_reset(): JTAG reset with TLR instead of TRST
Debug: 358 678 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 359 943 core.c:830 jtag_add_reset(): SRST line released
Debug: 361 1367 core.c:1578 jtag_init_inner(): Init JTAG chain
Debug: 362 1367 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 363 1367 core.c:1243 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 364 1367 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 365 1368 core.c:1142 jtag_examine_chain_display(): JTAG tap: zynq.tap tap/device found: 0x1372c093 (mfg: 0x049 (Xilinx), part: 0x372c, ver: 0x1)
Info : 366 1369 core.c:1142 jtag_examine_chain_display(): JTAG tap: zynq.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4)
Debug: 367 1369 core.c:1374 jtag_validate_ircapture(): IR capture validation scan
Debug: 368 1369 core.c:1431 jtag_validate_ircapture(): zynq.tap: IR capture 0x11
Debug: 369 1369 core.c:1431 jtag_validate_ircapture(): zynq.dap: IR capture 0x01
Debug: 370 1369 command.c:146 script_debug(): command - transport select
Debug: 371 1369 command.c:146 script_debug(): command - zynq.cpu.0 cget -chain-position
Debug: 372 1369 command.c:146 script_debug(): command - jtag tapisenabled zynq.dap
Debug: 373 1369 command.c:146 script_debug(): command - zynq.cpu.0 invoke-event examine-start
Debug: 374 1369 command.c:146 script_debug(): command - zynq.cpu.0 arp_examine allow-defer
Debug: 375 1371 arm_adi_v5.c:898 dap_find_ap(): Found APB-AP at AP index: 1 (IDR=0x24770002)
Debug: 376 1372 arm_adi_v5.c:792 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 377 1372 arm_adi_v5.c:803 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 378 1374 cortex_a.c:2742 cortex_a_examine_first(): didr = 0x35137030
Debug: 379 1375 cortex_a.c:2743 cortex_a_examine_first(): cpuid = 0x413fc090
Debug: 380 1376 cortex_a.c:2752 cortex_a_examine_first(): target->coreid 0 DBGPRSR  0x1
Debug: 381 1377 cortex_a.c:2768 cortex_a_examine_first(): target->coreid 0 DBGOSLSR 0x0
Debug: 382 1378 cortex_a.c:2799 cortex_a_examine_first(): target->coreid 0 has security extensions
Debug: 383 1378 cortex_a.c:2838 cortex_a_examine_first(): Configured 6 hw breakpoints
Debug: 384 1382 command.c:146 script_debug(): command - zynq.cpu.0 invoke-event examine-end
Debug: 385 1382 command.c:146 script_debug(): command - transport select
Debug: 386 1382 command.c:146 script_debug(): command - zynq.cpu.1 cget -chain-position
Debug: 387 1382 command.c:146 script_debug(): command - jtag tapisenabled zynq.dap
Debug: 388 1382 command.c:146 script_debug(): command - zynq.cpu.1 invoke-event examine-start
Debug: 389 1382 command.c:146 script_debug(): command - zynq.cpu.1 arp_examine allow-defer
Debug: 390 1384 arm_adi_v5.c:898 dap_find_ap(): Found APB-AP at AP index: 1 (IDR=0x24770002)
Debug: 391 1385 arm_adi_v5.c:792 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 392 1385 arm_adi_v5.c:803 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 393 1387 cortex_a.c:2742 cortex_a_examine_first(): didr = 0x35137030
Debug: 394 1387 cortex_a.c:2743 cortex_a_examine_first(): cpuid = 0x413fc090
Debug: 395 1388 cortex_a.c:2752 cortex_a_examine_first(): target->coreid 1 DBGPRSR  0x1
Debug: 396 1389 cortex_a.c:2768 cortex_a_examine_first(): target->coreid 1 DBGOSLSR 0x0
Debug: 397 1390 cortex_a.c:2799 cortex_a_examine_first(): target->coreid 1 has security extensions
Debug: 398 1390 cortex_a.c:2838 cortex_a_examine_first(): Configured 6 hw breakpoints
Debug: 399 1394 command.c:146 script_debug(): command - zynq.cpu.1 invoke-event examine-end
Debug: 400 1394 command.c:146 script_debug(): command - zynq.cpu.0 invoke-event reset-assert-pre
Debug: 401 1394 command.c:146 script_debug(): command - zynq.cpu.1 invoke-event reset-assert-pre
Debug: 402 1394 command.c:146 script_debug(): command - transport select
Debug: 403 1394 command.c:146 script_debug(): command - zynq.cpu.0 cget -chain-position
Debug: 404 1395 command.c:146 script_debug(): command - jtag tapisenabled zynq.dap
Debug: 405 1395 command.c:146 script_debug(): command - zynq.cpu.0 arp_reset assert 1
Debug: 406 1395 target.c:2172 target_free_all_working_areas_restore(): freeing all working areas
Debug: 407 1395 cortex_a.c:1669 cortex_a_assert_reset():  
Debug: 408 1395 command.c:146 script_debug(): command - transport select
Debug: 409 1395 command.c:146 script_debug(): command - zynq.cpu.1 cget -chain-position
Debug: 410 1395 command.c:146 script_debug(): command - jtag tapisenabled zynq.dap
Debug: 411 1395 command.c:146 script_debug(): command - zynq.cpu.1 arp_reset assert 1
Debug: 412 1395 target.c:2172 target_free_all_working_areas_restore(): freeing all working areas
Debug: 413 1395 cortex_a.c:1669 cortex_a_assert_reset():  
Debug: 414 1395 command.c:146 script_debug(): command - zynq.cpu.0 invoke-event reset-assert-post
Debug: 415 1395 command.c:146 script_debug(): command - zynq.cpu.1 invoke-event reset-assert-post
Debug: 416 1395 command.c:146 script_debug(): command - zynq.cpu.0 invoke-event reset-deassert-pre
Debug: 417 1395 command.c:146 script_debug(): command - zynq.cpu.1 invoke-event reset-deassert-pre
Debug: 418 1395 command.c:146 script_debug(): command - transport select
Debug: 419 1395 command.c:146 script_debug(): command - zynq.cpu.0 cget -chain-position
Debug: 420 1395 command.c:146 script_debug(): command - jtag tapisenabled zynq.dap
Debug: 421 1395 command.c:146 script_debug(): command - zynq.cpu.0 arp_reset deassert 1
Debug: 422 1396 target.c:2172 target_free_all_working_areas_restore(): freeing all working areas
Debug: 423 1396 cortex_a.c:1710 cortex_a_deassert_reset():  
Warn : 424 1397 cortex_a.c:1723 cortex_a_deassert_reset(): zynq.cpu.0: ran after reset and before halt ...
Debug: 425 1398 command.c:146 script_debug(): command - transport select
Debug: 426 1398 command.c:146 script_debug(): command - zynq.cpu.1 cget -chain-position
Debug: 427 1398 command.c:146 script_debug(): command - jtag tapisenabled zynq.dap
Debug: 428 1398 command.c:146 script_debug(): command - zynq.cpu.1 arp_reset deassert 1
Debug: 429 1398 target.c:2172 target_free_all_working_areas_restore(): freeing all working areas
Debug: 430 1398 cortex_a.c:1710 cortex_a_deassert_reset():  
Debug: 431 1399 cortex_a.c:730 cortex_a_poll(): Target halted
Debug: 432 1399 cortex_a.c:1000 cortex_a_debug_entry(): dscr = 0x03086003
Debug: 433 1401 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 434 1403 arm_dpm.c:234 arm_dpm_read_reg(): READ: r0, 60000113
Debug: 435 1403 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee001e15
Debug: 436 1404 arm_dpm.c:234 arm_dpm_read_reg(): READ: r1, 0028c0b8
Debug: 437 1404 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xe10f0000
Debug: 438 1405 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 439 1406 armv4_5.c:496 arm_set_cpsr(): set CPSR 0x60000113: Supervisor mode, ARM state
Debug: 440 1406 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee002e15
Debug: 441 1407 arm_dpm.c:234 arm_dpm_read_reg(): READ: r2, 00000000
Debug: 442 1407 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee003e15
Debug: 443 1409 arm_dpm.c:234 arm_dpm_read_reg(): READ: r3, 0028c088
Debug: 444 1409 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee004e15
Debug: 445 1410 arm_dpm.c:234 arm_dpm_read_reg(): READ: r4, 0028c0d0
Debug: 446 1410 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee005e15
Debug: 447 1412 arm_dpm.c:234 arm_dpm_read_reg(): READ: r5, 11293e00
Debug: 448 1412 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee006e15
Debug: 449 1413 arm_dpm.c:234 arm_dpm_read_reg(): READ: r6, 00000000
Debug: 450 1413 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee007e15
Debug: 451 1415 arm_dpm.c:234 arm_dpm_read_reg(): READ: r7, 11293eb4
Debug: 452 1415 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee008e15
Debug: 453 1416 arm_dpm.c:234 arm_dpm_read_reg(): READ: r8, 11293e84
Debug: 454 1416 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee009e15
Debug: 455 1417 arm_dpm.c:234 arm_dpm_read_reg(): READ: r9, 11293ee0
Debug: 456 1417 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee00ae15
Debug: 457 1419 arm_dpm.c:234 arm_dpm_read_reg(): READ: r10, 0028c0bc
Debug: 458 1419 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee00be15
Debug: 459 1420 arm_dpm.c:234 arm_dpm_read_reg(): READ: r11, 11294008
Debug: 460 1420 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee00ce15
Debug: 461 1421 arm_dpm.c:234 arm_dpm_read_reg(): READ: r12, 0028c0d4
Debug: 462 1421 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee00de15
Debug: 463 1423 arm_dpm.c:234 arm_dpm_read_reg(): READ: sp_svc, 11293c68
Debug: 464 1423 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee00ee15
Debug: 465 1424 arm_dpm.c:234 arm_dpm_read_reg(): READ: lr_svc, 0017817c
Debug: 466 1424 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xe1a0000f
Debug: 467 1425 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 468 1426 arm_dpm.c:234 arm_dpm_read_reg(): READ: pc, 0017b170
Debug: 469 1426 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xe14f0000
Debug: 470 1427 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 471 1428 arm_dpm.c:234 arm_dpm_read_reg(): READ: spsr_svc, 00000000
Debug: 472 1429 arm_dpm.c:64 dpm_mrc(): MRC p15, 0, r0, c1, c0, 0
Debug: 473 1429 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee110f10
Debug: 474 1429 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 475 1431 cortex_a.c:1084 cortex_a_post_debug_entry(): cp15_control_reg: 08c5187d
Debug: 476 1431 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee120f50
Debug: 477 1432 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 478 1433 armv7a.c:147 armv7a_read_ttbcr(): ttbcr 0
Debug: 479 1433 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee120f10
Debug: 480 1434 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 481 1435 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee120f30
Debug: 482 1436 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 483 1438 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100f10
Debug: 484 1439 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Info : 485 1440 armv7a.c:114 armv7a_read_midr(): zynq.cpu.1 rev 0, partnum c09, arch f, variant 3, implementor 41
Debug: 486 1440 armv7a.c:182 armv7a_read_ttbcr(): ttbr1 not used, ttbr0_mask ffffc000 ttbr1_mask ffffc000
Debug: 487 1440 cortex_a.c:343 cortex_a_write_dcc(): write DCC 0x00000013
Debug: 488 1440 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100e15
Debug: 489 1441 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xe12ff000
Debug: 490 1442 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee070f95
Debug: 491 1443 arm_dpm.c:64 dpm_mrc(): MRC p15, 0, r0, c3, c0, 0
Debug: 492 1443 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee130f10
Debug: 493 1444 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee000e15
Debug: 494 1445 cortex_a.c:1111 cortex_a_post_debug_entry(): cp15_dacr_reg: ffffffff
Debug: 495 1445 cortex_a.c:343 cortex_a_write_dcc(): write DCC 0x60000113
Debug: 496 1445 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee100e15
Debug: 497 1446 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xe12ff000
Debug: 498 1447 cortex_a.c:287 cortex_a_exec_opcode(): exec opcode 0xee070f95
Error: 501 2449 cortex_a.c:1782 cortex_a_wait_dscr_bits(): timeout waiting for DSCR bit change
Error: 502 2449 cortex_a.c:778 cortex_a_halt(): Error waiting for halt
Debug: 503 2450 command.c:628 run_command(): Command 'reset' failed with error code -4
User : 504 2450 command.c:694 command_run_line(): 
Debug: 505 2451 target.c:2172 target_free_all_working_areas_restore(): freeing all working areas
Debug: 506 2452 target.c:2172 target_free_all_working_areas_restore(): freeing all working areas