diff --git a/artiq/coredevice/phaser.py b/artiq/coredevice/phaser.py index 5f3c4c33..97b32d25 100644 --- a/artiq/coredevice/phaser.py +++ b/artiq/coredevice/phaser.py @@ -173,7 +173,7 @@ class Phaser: tune_fifo_offset: Kernel[bool] sync_dly: Kernel[int32] dac_mmap: KernelInvariant[list[int32]] - channel: Kernel[list[PhaserChannel]] + #channel: Kernel[list[PhaserChannel]] def __init__(self, dmgr, channel_base, miso_delay=1, tune_fifo_offset=True, clk_sel=False, sync_dly=0, dac=None, trf0=None, trf1=None, @@ -193,8 +193,8 @@ class Phaser: self.dac_mmap = DAC34H84(dac).get_mmap() - self.channel = [PhaserChannel(self, ch, trf) - for ch, trf in enumerate([trf0, trf1])] + #self.channel = [PhaserChannel(self, ch, trf) + # for ch, trf in enumerate([trf0, trf1])] @kernel def init(self, debug: bool = False): @@ -326,62 +326,62 @@ class Phaser: # power up trfs, release att reset self.set_cfg(clk_sel=self.clk_sel, dac_txena=False) - for ch in range(2): - channel = self.channel[ch] - # test attenuator write and readback - channel.set_att_mu(0x5a) - if channel.get_att_mu() != 0x5a: - raise ValueError("attenuator test failed") - self.core.delay(.1*ms) - channel.set_att_mu(0x00) # minimum attenuation - - # test oscillators and DUC - for i in range(len(channel.oscillator)): - oscillator = channel.oscillator[i] - asf = 0 - if i == 0: - asf = 0x7fff - # 6pi/4 phase - oscillator.set_amplitude_phase_mu(asf=asf, pow=0xc000, clr=True) - self.core.delay(1.*us) - # 3pi/4 - channel.set_duc_phase_mu(0x6000) - channel.set_duc_cfg(select=0, clr=True) - self.duc_stb() - self.core.delay(.1*ms) # settle link, pipeline and impulse response - data = channel.get_dac_data() - self.core.delay(1.*us) - channel.oscillator[0].set_amplitude_phase_mu(asf=0, pow=0xc000, - clr=True) - self.core.delay(.1*ms) - sqrt2 = 0x5a81 # 0x7fff/sqrt(2) - data_i = data & 0xffff - data_q = (data >> 16) & 0xffff - # allow ripple - if (data_i < sqrt2 - 30 or data_i > sqrt2 or - abs(data_i - data_q) > 2): - raise ValueError("DUC+oscillator phase/amplitude test failed") - - if is_baseband: - continue - - if channel.trf_read(0) & 0x7f != 0x68: - raise ValueError("TRF identification failed") - self.core.delay(.1*ms) - - self.core.delay(.2*ms) - for data in channel.trf_mmap: - channel.trf_write(data) - channel.cal_trf_vco() - - self.core.delay(2.*ms) # lock - if not (self.get_sta() & (PHASER_STA_TRF0_LD << ch)): - raise ValueError("TRF lock failure") - self.core.delay(.1*ms) - if channel.trf_read(0) & 0x1000 != 0: - raise ValueError("TRF R_SAT_ERR") - self.core.delay(.1*ms) - channel.en_trf_out() + # for ch in range(2): + # channel = self.channel[ch] + # # test attenuator write and readback + # channel.set_att_mu(0x5a) + # if channel.get_att_mu() != 0x5a: + # raise ValueError("attenuator test failed") + # self.core.delay(.1*ms) + # channel.set_att_mu(0x00) # minimum attenuation + + # # test oscillators and DUC + # for i in range(len(channel.oscillator)): + # oscillator = channel.oscillator[i] + # asf = 0 + # if i == 0: + # asf = 0x7fff + # # 6pi/4 phase + # oscillator.set_amplitude_phase_mu(asf=asf, pow=0xc000, clr=True) + # self.core.delay(1.*us) + # # 3pi/4 + # channel.set_duc_phase_mu(0x6000) + # channel.set_duc_cfg(select=0, clr=True) + # self.duc_stb() + # self.core.delay(.1*ms) # settle link, pipeline and impulse response + # data = channel.get_dac_data() + # self.core.delay(1.*us) + # channel.oscillator[0].set_amplitude_phase_mu(asf=0, pow=0xc000, + # clr=True) + # self.core.delay(.1*ms) + # sqrt2 = 0x5a81 # 0x7fff/sqrt(2) + # data_i = data & 0xffff + # data_q = (data >> 16) & 0xffff + # # allow ripple + # if (data_i < sqrt2 - 30 or data_i > sqrt2 or + # abs(data_i - data_q) > 2): + # raise ValueError("DUC+oscillator phase/amplitude test failed") + + # if is_baseband: + # continue + + # if channel.trf_read(0) & 0x7f != 0x68: + # raise ValueError("TRF identification failed") + # self.core.delay(.1*ms) + + # self.core.delay(.2*ms) + # for data in channel.trf_mmap: + # channel.trf_write(data) + # channel.cal_trf_vco() + + # self.core.delay(2.*ms) # lock + # if not (self.get_sta() & (PHASER_STA_TRF0_LD << ch)): + # raise ValueError("TRF lock failure") + # self.core.delay(.1*ms) + # if channel.trf_read(0) & 0x1000 != 0: + # raise ValueError("TRF R_SAT_ERR") + # self.core.delay(.1*ms) + # channel.en_trf_out() # enable dac tx self.set_cfg(clk_sel=self.clk_sel) @@ -695,15 +695,15 @@ class Phaser: # repeat the pattern twice self.dac_write(0x29 + addr, pattern[addr]) self.core.delay(.1*ms) - for ch in range(2): - channel = self.channel[ch] - channel.set_duc_cfg(select=1) # test - # dac test data is i msb, q lsb - data = pattern[2*ch] | (pattern[2*ch + 1] << 16) - channel.set_dac_test(data) - if channel.get_dac_data() != data: - raise ValueError("DAC test data readback failed") - self.core.delay(.1*ms) + # for ch in range(2): + # channel = self.channel[ch] + # channel.set_duc_cfg(select=1) # test + # # dac test data is i msb, q lsb + # data = pattern[2*ch] | (pattern[2*ch + 1] << 16) + # channel.set_dac_test(data) + # if channel.get_dac_data() != data: + # raise ValueError("DAC test data readback failed") + # self.core.delay(.1*ms) cfg = self.dac_read(0x01) self.core.delay(.1*ms) self.dac_write(0x01, cfg | 0x8000) # iotest_ena diff --git a/artiq/examples/nac3devices/nac3devices.py b/artiq/examples/nac3devices/nac3devices.py index 396da3fd..79b4815f 100644 --- a/artiq/examples/nac3devices/nac3devices.py +++ b/artiq/examples/nac3devices/nac3devices.py @@ -26,7 +26,7 @@ class NAC3Devices(EnvExperiment): ttl0_counter: KernelInvariant[EdgeCounter] grabber0: KernelInvariant[Grabber] fastino0: KernelInvariant[Fastino] - # NAC3TODO segfault phaser0: KernelInvariant[Fastino] + phaser0: KernelInvariant[Phaser] def build(self): self.setattr_device("core") @@ -40,7 +40,7 @@ class NAC3Devices(EnvExperiment): self.setattr_device("ttl0_counter") self.setattr_device("grabber0") self.setattr_device("fastino0") - # NAC3TODO segfault self.setattr_device("phaser0") + self.setattr_device("phaser0") @kernel def run(self):