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suservo: reorder EEM pins

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- Assign MISO to EEM0[2];
- Move NU_CLK to EEM0[5];
- Remove NU_CS.
This commit is contained in:
occheung
2025-10-14 16:58:26 +08:00
parent 8b439eac02
commit d14eba7311
2 changed files with 27 additions and 25 deletions
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28
ice40/urukul.py
View File

@@ -226,12 +226,12 @@ class Urukul(Module):
|------+-----------+---------+---------------------+-----------|
| EEM0 | 0 | A0 | SCLK | SCLK |
| EEM0 | 1 | A1 | MOSI | MOSI |
| EEM0 | 2 | A2 | MISO | NU_CLK |
| EEM0 | 2 | A2 | MISO | MISO |
| EEM0 | 3 | A3 | CS0 | CS0 |
| EEM0 | 4 | A4 | CS1 | CS1 |
| EEM0 | 5 | A5 | CS2 | NU_CS |
| EEM0 | 5 | A5 | CS2 | NU_CLK |
| EEM0 | 6 | A6 | IO_UPDATE | IO_UPDATE |
| EEM0 | 7 | A7 | DDS_RESET, SYNC_IN | DDS_RESET |
| EEM0 | 7 | A7 | DDS_RESET, SYNC_IN | SYNC_IN |
| EEM1 | 0 | B8 | SYNC_CLK | NU_MOSI0 |
| EEM1 | 1 | B9 | SYNC_OUT | NU_MOSI1 |
| EEM1 | 2 | B10 | IO_UPDATE_RET | NU_MOSI2 |
@@ -267,9 +267,9 @@ class Urukul(Module):
An SPI interface is provided to access any of the six serial devices (the
configuration/status SPI interface, the attenuator SPI interface, and the
four DDS SPI interfaces). It comprises the SCLK, MOSI, MISO, CS0, CS1, and
CS2 signals. In the SU-Servo mode, both MISO and CS2 (and the functionality
provided by them) are unavailable. I.e. CS >= 4 (individual DDS access)
are only available outside of the SU-Servo mode or through CS = 3 (and
CS2 signals. In the SU-Servo mode, CS2 (and the functionality provided by
it) is unavailable. I.e. CS >= 4 (individual DDS access) are only
available outside of the SU-Servo mode or through CS = 3 (and
CFG.MASK_NU).
The target chip (or set of chips) is selected by CS0/CS1/CS2 (CS2 being the
@@ -327,14 +327,14 @@ class Urukul(Module):
----
In the SU-Servo mode, the four DDS are additionally exposed through a
quad-SPI write-only interface defined by the signals NU_CLK, NU_CS, and
quad-SPI write-only interface defined by the signals NU_CLK, and
NU_MOSI[0:3].
Only those DDS which are **not** masked by CFG.MASK_NU can be accessed
through the QSPI interface. This allows initial setup and configuration of
the DDS individually through the "regular" SPI interface in this mode.
DDS[0:3].CS is driven by NU_CS (for those DDS not masked)
DDS[0:3].CS_N is tied to 0 (for those DDS not masked)
DDS[0:3].SCK is driven by NU_CLK (for those DDS not masked)
DDS[0:3].MOSI is driven by NU_MOSI[0:3] (for those DDS not masked)
DDS[0:3].MISO is unavailable
@@ -446,7 +446,6 @@ class Urukul(Module):
io_update = Signal()
dds_reset = Signal()
nu_mosi = Signal(4)
nu_sel = Signal()
self.specials += [
Instance("SB_GB_IO",
@@ -455,6 +454,7 @@ class Urukul(Module):
io_PACKAGE_PIN=eem[0],
o_GLOBAL_BUFFER_OUTPUT=self.cd_sck1.clk),
DifferentialInput(eem[1], Signal(), mosi),
DifferentialOutput(miso_phy, eem[2], platform.request("eem_n", 2)),
DifferentialInput(eem[6], Signal(), io_update),
DifferentialInput(eem[7], Signal(), dds_reset),
]
@@ -463,15 +463,13 @@ class Urukul(Module):
if enable_suservo:
self.specials += [
DifferentialInput(eem[2], Signal(), nu_clk),
DifferentialInput(eem[5], Signal(), nu_sel),
*[DifferentialInput(eem[8 + i], Signal(), nu_mosi[i]) for i in range(4)]
DifferentialInput(eem[5], Signal(), nu_clk),
*[ DifferentialInput(eem[8 + i], Signal(), nu_mosi[i]) for i in range(4) ]
]
cs = Signal(2)
else:
self.specials += [
DifferentialOutput(miso_phy, eem[2], platform.request("eem_n", 2)),
Instance("SB_IO",
p_PIN_TYPE=C(0b101000, 6),
p_IO_STANDARD="SB_LVCMOS",
@@ -555,7 +553,9 @@ class Urukul(Module):
sel_spi.eq(sel[i + 4] | (sel[3] & cfg.data.mask_nu[i])),
sel_nu.eq(enable_suservo & ~cfg.data.mask_nu[i]),
ddsi.sdi.eq(Mux(sel_nu, nu_mosi[i], mosi)),
ddsi.cs_n.eq(~Mux(sel_nu, nu_sel, sel_spi)),
# NU_CLK exclusively drive SCLK in SU-Servo mode.
# As per the AD9910 datasheet, CS_N can be tied low.
ddsi.cs_n.eq(~Mux(sel_nu, 1, sel_spi)),
ddsi.sck.eq(Mux(sel_nu, nu_clk, self.cd_sck1.clk)),
miso[i + 4].eq(ddsi.sdo),
ddsi.io_update.eq(Mux(cfg.data.mask_nu[i],

24
xc2c/urukul.py
View File

@@ -228,10 +228,10 @@ class Urukul(Module):
|------+-----------+---------+-------------------------|
| EEM0 | 0 | A0 | SCLK |
| EEM0 | 1 | A1 | MOSI |
| EEM0 | 2 | A2 | MISO, NU_CLK |
| EEM0 | 2 | A2 | MISO |
| EEM0 | 3 | A3 | CS0 |
| EEM0 | 4 | A4 | CS1 |
| EEM0 | 5 | A5 | CS2, NU_CS |
| EEM0 | 5 | A5 | CS2, NU_CLK |
| EEM0 | 6 | A6 | IO_UPDATE |
| EEM0 | 7 | A7 | DDS_RESET, SYNC_OUT |
| EEM1 | 0 | B8 | SYNC_CLK, NU_MOSI0 |
@@ -267,9 +267,9 @@ class Urukul(Module):
An SPI interface is provided to access any of the six serial devices (the
configuration/status SPI interface, the attenuator SPI interface, and the
four DDS SPI interfaces). It comprises the SCLK, MOSI, MISO, CS0, CS1, and
CS2 signals. With EN_NU, both MISO and CS2 (and the functionality provided
by them) are unavailable. I.e. CS >= 4 (the individual DDS access) are only
available outside of EN_NU or through CS = 3 (and CFG.MASK_NU).
CS2 signals. With EN_NU, CS2 (and the functionality provided by it) is
unavailable. I.e. CS >= 4 (the individual DDS access) are only available
outside of EN_NU or through CS = 3 (and CFG.MASK_NU).
The target chip (or set of chips) is selected by CS0/CS1/CS2 (CS2 being the
MSB). The encoding is as follows:
@@ -326,14 +326,14 @@ class Urukul(Module):
----
If EN_NU is activated, the four DDS are additionally exposed through a
quad-SPI write-only interface defined by the signals NU_CLK, NU_CS, and
quad-SPI write-only interface defined by the signals NU_CLK, and
NU_MOSI[0:3].
Only those DDS which are **not** masked by CFG.MASK_NU can be accessed
through the QSPI interface. This allows initial setup and configuration of
the DDS individually through the "regular" SPI interface in EN_NU mode.
DDS[0:3].CS is driven by NU_CS (for those DDS not masked)
DDS[0:3].CS_N is tied to 0 (for those DDS not masked)
DDS[0:3].SCK is driven by NU_CLK (for those DDS not masked)
DDS[0:3].MOSI is driven by NU_MOSI[0:3] (for those DDS not masked)
DDS[0:3].MISO is unavailable
@@ -440,7 +440,7 @@ class Urukul(Module):
self.clock_domains.cd_sck1 = ClockDomain("sck1", reset_less=True)
platform.add_period_constraint(eem[0]._pin, 8.)
platform.add_period_constraint(eem[2]._pin, 8.)
platform.add_period_constraint(eem[5]._pin, 8.)
self.specials += [
Instance("BUFG", i_I=eem[0].i, o_O=self.cd_sck1.clk),
@@ -456,7 +456,7 @@ class Urukul(Module):
en_nu.eq(ifc_mode[1]),
en_eem1.eq(ifc_mode[2]),
[eem[i].oe.eq(0) for i in range(12) if i not in (2, 10)],
eem[2].oe.eq(~en_nu),
eem[2].oe.eq(1),
eem[10].oe.eq(~en_nu & en_eem1),
eem[10].o.eq(eem[6].i),
self.cd_sck0.clk.eq(~self.cd_sck1.clk),
@@ -531,8 +531,10 @@ class Urukul(Module):
self.comb += [
sel_spi.eq(sel[i + 4] | (sel[3] & cfg.data.mask_nu[i])),
sel_nu.eq(en_nu & ~cfg.data.mask_nu[i]),
ddsi.cs_n.eq(~Mux(sel_nu, eem[5].i, sel_spi)),
ddsi.sck.eq(Mux(sel_nu, eem[2].i, self.cd_sck1.clk)),
# NU_CLK exclusively drive SCLK in SU-Servo mode.
# As per the AD9910 datasheet, CS_N can be tied low.
ddsi.cs_n.eq(~Mux(sel_nu, 1, sel_spi)),
ddsi.sck.eq(Mux(sel_nu, eem[5].i, self.cd_sck1.clk)),
ddsi.sdi.eq(Mux(sel_nu, eem[i + 8].i, mosi)),
miso[i + 4].eq(ddsi.sdo),
ddsi.io_update.eq(Mux(cfg.data.mask_nu[i],