2020-03-12 06:16:48 +08:00
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use stm32f4xx_hal::{
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2020-04-11 03:05:05 +08:00
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adc::Adc,
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2020-03-12 06:16:48 +08:00
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gpio::{
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2020-09-24 06:16:40 +08:00
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AF5, Alternate, AlternateOD, Analog, Floating, Input,
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2020-03-13 00:26:14 +08:00
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gpioa::*,
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gpiob::*,
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gpioc::*,
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gpioe::*,
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2020-03-13 02:24:57 +08:00
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gpiof::*,
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2020-03-13 00:26:14 +08:00
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gpiog::*,
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2020-03-12 06:16:48 +08:00
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GpioExt,
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Output, PushPull,
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},
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2020-09-24 06:16:40 +08:00
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hal::{self, blocking::spi::Transfer, digital::v2::OutputPin},
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i2c::I2c,
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2020-09-11 05:17:31 +08:00
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otg_fs::USB,
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2020-03-12 06:16:48 +08:00
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rcc::Clocks,
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2020-03-13 00:26:14 +08:00
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pwm::{self, PwmChannels},
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2022-01-25 12:47:31 +08:00
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spi::{Spi, NoMiso, TransferModeNormal},
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pac::{
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2020-09-11 05:17:31 +08:00
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ADC1,
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GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG,
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2020-09-24 06:16:40 +08:00
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I2C1,
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2020-09-11 05:17:31 +08:00
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OTG_FS_GLOBAL, OTG_FS_DEVICE, OTG_FS_PWRCLK,
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SPI2, SPI4, SPI5,
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2023-03-22 17:15:49 +08:00
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TIM1, TIM3, TIM8
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2020-09-11 05:17:31 +08:00
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},
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2022-01-25 12:47:31 +08:00
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timer::Timer,
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2020-03-20 05:21:17 +08:00
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time::U32Ext,
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2020-03-09 07:27:35 +08:00
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};
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2020-09-24 06:16:40 +08:00
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use eeprom24x::{self, Eeprom24x};
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2020-09-04 03:38:56 +08:00
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use stm32_eth::EthPins;
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2020-09-07 03:10:10 +08:00
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use crate::{
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channel::{Channel0, Channel1},
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leds::Leds,
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2023-03-22 17:15:49 +08:00
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fan_ctrl::FanPin,
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hw_rev::{HWRev, HWSettings},
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2020-09-07 03:10:10 +08:00
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};
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2020-03-09 07:27:35 +08:00
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2020-09-24 06:16:40 +08:00
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pub type Eeprom = Eeprom24x<
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I2c<I2C1, (
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2022-01-25 12:47:31 +08:00
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PB8<AlternateOD<{ stm32f4xx_hal::gpio::AF4 }>>,
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PB9<AlternateOD<{ stm32f4xx_hal::gpio::AF4 }>>
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2020-09-24 06:16:40 +08:00
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)>,
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eeprom24x::page_size::B8,
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eeprom24x::addr_size::OneByte
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>;
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2020-03-12 06:16:48 +08:00
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2020-09-04 03:38:56 +08:00
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pub type EthernetPins = EthPins<
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PA1<Input<Floating>>,
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PA7<Input<Floating>>,
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PB11<Input<Floating>>,
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PG13<Input<Floating>>,
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PB13<Input<Floating>>,
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PC4<Input<Floating>>,
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PC5<Input<Floating>>,
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>;
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2020-05-13 05:16:57 +08:00
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pub trait ChannelPins {
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type DacSpi: Transfer<u8>;
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type DacSync: OutputPin;
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type Shdn: OutputPin;
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2020-05-19 04:43:44 +08:00
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type VRefPin;
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2024-04-03 15:58:15 +08:00
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type ITecPin;
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2020-05-17 08:18:25 +08:00
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type DacFeedbackPin;
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2020-05-19 03:38:13 +08:00
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type TecUMeasPin;
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2020-05-13 05:16:57 +08:00
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}
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2024-02-28 16:35:20 +08:00
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pub enum Channel0VRef {
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Analog(PA0<Analog>),
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Disabled(PA0<Input<Floating>>),
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}
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2020-05-13 05:16:57 +08:00
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impl ChannelPins for Channel0 {
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type DacSpi = Dac0Spi;
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type DacSync = PE4<Output<PushPull>>;
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type Shdn = PE10<Output<PushPull>>;
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2024-02-28 16:35:20 +08:00
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type VRefPin = Channel0VRef;
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2024-04-03 15:58:15 +08:00
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type ITecPin = PA6<Analog>;
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2020-05-17 08:18:25 +08:00
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type DacFeedbackPin = PA4<Analog>;
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2020-05-19 03:38:13 +08:00
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type TecUMeasPin = PC2<Analog>;
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2020-05-13 05:16:57 +08:00
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}
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2024-02-28 16:35:20 +08:00
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pub enum Channel1VRef {
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Analog(PA3<Analog>),
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Disabled(PA3<Input<Floating>>),
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}
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2020-05-13 05:16:57 +08:00
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impl ChannelPins for Channel1 {
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type DacSpi = Dac1Spi;
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type DacSync = PF6<Output<PushPull>>;
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type Shdn = PE15<Output<PushPull>>;
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2024-02-28 16:35:20 +08:00
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type VRefPin = Channel1VRef;
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2024-04-03 15:58:15 +08:00
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type ITecPin = PB0<Analog>;
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2020-05-17 08:18:25 +08:00
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type DacFeedbackPin = PA5<Analog>;
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2020-05-19 03:38:13 +08:00
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type TecUMeasPin = PC3<Analog>;
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2020-05-13 05:16:57 +08:00
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}
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2020-03-12 06:16:48 +08:00
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/// SPI peripheral used for communication with the ADC
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2022-01-25 12:47:31 +08:00
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pub type AdcSpi = Spi<SPI2, (PB10<Alternate<AF5>>, PB14<Alternate<AF5>>, PB15<Alternate<AF5>>), TransferModeNormal>;
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2020-05-13 05:16:57 +08:00
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pub type AdcNss = PB12<Output<PushPull>>;
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2022-01-25 12:47:31 +08:00
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type Dac0Spi = Spi<SPI4, (PE2<Alternate<AF5>>, NoMiso, PE6<Alternate<AF5>>), TransferModeNormal>;
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type Dac1Spi = Spi<SPI5, (PF7<Alternate<AF5>>, NoMiso, PF9<Alternate<AF5>>), TransferModeNormal>;
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2020-05-28 08:01:55 +08:00
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pub type PinsAdc = Adc<ADC1>;
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2020-03-13 02:24:57 +08:00
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2020-05-13 05:16:57 +08:00
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pub struct ChannelPinSet<C: ChannelPins> {
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pub dac_spi: C::DacSpi,
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pub dac_sync: C::DacSync,
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pub shdn: C::Shdn,
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2020-05-19 04:43:44 +08:00
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pub vref_pin: C::VRefPin,
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2024-04-03 15:58:15 +08:00
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pub itec_pin: C::ITecPin,
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2020-05-17 08:18:25 +08:00
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pub dac_feedback_pin: C::DacFeedbackPin,
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2020-05-19 03:38:13 +08:00
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pub tec_u_meas_pin: C::TecUMeasPin,
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2020-05-13 05:16:57 +08:00
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}
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2023-03-22 17:15:49 +08:00
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pub struct HWRevPins {
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pub hwrev0: stm32f4xx_hal::gpio::gpiod::PD0<Input<Floating>>,
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pub hwrev1: stm32f4xx_hal::gpio::gpiod::PD1<Input<Floating>>,
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pub hwrev2: stm32f4xx_hal::gpio::gpiod::PD2<Input<Floating>>,
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pub hwrev3: stm32f4xx_hal::gpio::gpiod::PD3<Input<Floating>>,
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}
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2020-03-12 06:16:48 +08:00
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pub struct Pins {
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pub adc_spi: AdcSpi,
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2020-05-13 05:16:57 +08:00
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pub adc_nss: AdcNss,
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2020-05-28 08:01:55 +08:00
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pub pins_adc: PinsAdc,
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2020-03-13 00:26:14 +08:00
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pub pwm: PwmPins,
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2020-05-13 05:16:57 +08:00
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pub channel0: ChannelPinSet<Channel0>,
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pub channel1: ChannelPinSet<Channel1>,
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2020-03-12 06:16:48 +08:00
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}
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impl Pins {
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/// Setup GPIO pins and configure MCU peripherals
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2020-03-13 00:26:14 +08:00
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pub fn setup(
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clocks: Clocks,
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2023-03-22 17:15:49 +08:00
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tim1: TIM1, tim3: TIM3, tim8: TIM8,
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2020-09-07 03:10:10 +08:00
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gpioa: GPIOA, gpiob: GPIOB, gpioc: GPIOC, gpiod: GPIOD, gpioe: GPIOE, gpiof: GPIOF, gpiog: GPIOG,
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2020-09-24 06:16:40 +08:00
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i2c1: I2C1,
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2020-04-11 03:05:05 +08:00
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spi2: SPI2, spi4: SPI4, spi5: SPI5,
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2020-05-28 08:06:32 +08:00
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adc1: ADC1,
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2020-09-11 05:17:31 +08:00
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otg_fs_global: OTG_FS_GLOBAL, otg_fs_device: OTG_FS_DEVICE, otg_fs_pwrclk: OTG_FS_PWRCLK,
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2023-03-22 17:15:49 +08:00
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) -> (Self, Leds, Eeprom, EthernetPins, USB, Option<FanPin>, HWRev, HWSettings) {
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2020-03-12 06:16:48 +08:00
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let gpioa = gpioa.split();
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let gpiob = gpiob.split();
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let gpioc = gpioc.split();
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2020-09-07 03:10:10 +08:00
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let gpiod = gpiod.split();
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2020-03-13 00:26:14 +08:00
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let gpioe = gpioe.split();
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2020-03-13 02:24:57 +08:00
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let gpiof = gpiof.split();
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2020-03-12 06:16:48 +08:00
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let gpiog = gpiog.split();
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let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15);
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let adc_nss = gpiob.pb12.into_push_pull_output();
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2020-03-13 00:26:14 +08:00
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2020-05-28 08:01:55 +08:00
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let pins_adc = Adc::adc1(adc1, true, Default::default());
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2020-05-19 03:38:13 +08:00
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2020-03-21 07:33:31 +08:00
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let pwm = PwmPins::setup(
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clocks, tim1, tim3,
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gpioc.pc6, gpioc.pc7,
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gpioe.pe9, gpioe.pe11,
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gpioe.pe13, gpioe.pe14
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);
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2024-02-28 16:35:20 +08:00
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let hwrev = HWRev::detect_hw_rev(&HWRevPins {hwrev0: gpiod.pd0, hwrev1: gpiod.pd1,
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hwrev2: gpiod.pd2, hwrev3: gpiod.pd3});
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let hw_settings = hwrev.settings();
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2020-03-13 02:24:57 +08:00
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let (dac0_spi, dac0_sync) = Self::setup_dac0(
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clocks, spi4,
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gpioe.pe2, gpioe.pe4, gpioe.pe6
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);
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2020-03-21 07:33:31 +08:00
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let mut shdn0 = gpioe.pe10.into_push_pull_output();
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let _ = shdn0.set_low();
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2024-02-28 16:35:20 +08:00
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let vref0_pin = if hwrev.major > 2 {Channel0VRef::Analog(gpioa.pa0.into_analog())} else {Channel0VRef::Disabled(gpioa.pa0)};
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2020-05-17 05:59:31 +08:00
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let itec0_pin = gpioa.pa6.into_analog();
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2020-05-17 08:18:25 +08:00
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let dac_feedback0_pin = gpioa.pa4.into_analog();
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2020-05-19 03:38:13 +08:00
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let tec_u_meas0_pin = gpioc.pc2.into_analog();
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2020-05-13 05:16:57 +08:00
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let channel0 = ChannelPinSet {
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dac_spi: dac0_spi,
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dac_sync: dac0_sync,
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shdn: shdn0,
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2020-05-19 04:43:44 +08:00
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vref_pin: vref0_pin,
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2020-05-17 05:59:31 +08:00
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itec_pin: itec0_pin,
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2020-05-17 08:18:25 +08:00
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dac_feedback_pin: dac_feedback0_pin,
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2020-05-19 03:38:13 +08:00
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tec_u_meas_pin: tec_u_meas0_pin,
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2020-05-13 05:16:57 +08:00
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};
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2020-04-11 03:05:05 +08:00
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2020-03-13 02:24:57 +08:00
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let (dac1_spi, dac1_sync) = Self::setup_dac1(
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clocks, spi5,
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gpiof.pf7, gpiof.pf6, gpiof.pf9
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);
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2020-03-21 07:33:31 +08:00
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let mut shdn1 = gpioe.pe15.into_push_pull_output();
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let _ = shdn1.set_low();
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2024-02-28 16:35:20 +08:00
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let vref1_pin = if hwrev.major > 2 {Channel1VRef::Analog(gpioa.pa3.into_analog())} else {Channel1VRef::Disabled(gpioa.pa3)};
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2020-05-17 05:59:31 +08:00
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let itec1_pin = gpiob.pb0.into_analog();
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2020-05-17 08:18:25 +08:00
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let dac_feedback1_pin = gpioa.pa5.into_analog();
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2020-05-19 03:38:13 +08:00
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let tec_u_meas1_pin = gpioc.pc3.into_analog();
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2020-05-13 05:16:57 +08:00
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let channel1 = ChannelPinSet {
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dac_spi: dac1_spi,
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dac_sync: dac1_sync,
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shdn: shdn1,
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2020-05-19 04:43:44 +08:00
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vref_pin: vref1_pin,
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2020-05-17 05:59:31 +08:00
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itec_pin: itec1_pin,
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2020-05-17 08:18:25 +08:00
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dac_feedback_pin: dac_feedback1_pin,
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2020-05-19 03:38:13 +08:00
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tec_u_meas_pin: tec_u_meas1_pin,
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2020-05-13 05:16:57 +08:00
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};
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2020-03-13 00:26:14 +08:00
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2020-09-04 03:38:56 +08:00
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let pins = Pins {
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2020-03-13 02:24:57 +08:00
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adc_spi, adc_nss,
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2020-05-28 08:06:32 +08:00
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pins_adc,
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2020-03-13 00:26:14 +08:00
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pwm,
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2020-05-13 05:16:57 +08:00
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channel0,
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channel1,
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2020-09-04 03:38:56 +08:00
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};
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2020-09-07 03:10:10 +08:00
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let leds = Leds::new(gpiod.pd9, gpiod.pd10.into_push_pull_output(), gpiod.pd11.into_push_pull_output());
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2022-01-25 12:47:31 +08:00
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let eeprom_scl = gpiob.pb8.into_alternate().set_open_drain();
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let eeprom_sda = gpiob.pb9.into_alternate().set_open_drain();
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let eeprom_i2c = I2c::new(i2c1, (eeprom_scl, eeprom_sda), 400.khz(), clocks);
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2020-09-24 06:16:40 +08:00
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let eeprom = Eeprom24x::new_24x02(eeprom_i2c, eeprom24x::SlaveAddr::default());
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2020-09-04 03:38:56 +08:00
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let eth_pins = EthPins {
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ref_clk: gpioa.pa1,
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crs: gpioa.pa7,
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tx_en: gpiob.pb11,
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tx_d0: gpiog.pg13,
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tx_d1: gpiob.pb13,
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rx_d0: gpioc.pc4,
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rx_d1: gpioc.pc5,
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};
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2020-09-11 05:17:31 +08:00
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let usb = USB {
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usb_global: otg_fs_global,
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usb_device: otg_fs_device,
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usb_pwrclk: otg_fs_pwrclk,
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2022-01-25 12:47:31 +08:00
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pin_dm: gpioa.pa11.into_alternate(),
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pin_dp: gpioa.pa12.into_alternate(),
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2020-09-11 05:17:31 +08:00
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hclk: clocks.hclk(),
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};
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2023-03-22 17:15:49 +08:00
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let fan = if hw_settings.fan_available {
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Some(Timer::new(tim8, &clocks).pwm(gpioc.pc9.into_alternate(), hw_settings.fan_pwm_freq_hz.hz()))
|
|
|
|
} else { None };
|
|
|
|
|
|
|
|
(pins, leds, eeprom, eth_pins, usb, fan, hwrev, hw_settings)
|
2020-03-12 06:16:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Configure the GPIO pins for SPI operation, and initialize SPI
|
|
|
|
fn setup_spi_adc<M1, M2, M3>(
|
|
|
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clocks: Clocks,
|
|
|
|
spi2: SPI2,
|
|
|
|
sck: PB10<M1>,
|
|
|
|
miso: PB14<M2>,
|
|
|
|
mosi: PB15<M3>,
|
|
|
|
) -> AdcSpi
|
|
|
|
{
|
2022-01-25 12:47:31 +08:00
|
|
|
let sck = sck.into_alternate();
|
|
|
|
let miso = miso.into_alternate();
|
|
|
|
let mosi = mosi.into_alternate();
|
|
|
|
Spi::new(
|
2020-03-12 06:16:48 +08:00
|
|
|
spi2,
|
|
|
|
(sck, miso, mosi),
|
|
|
|
crate::ad7172::SPI_MODE,
|
2022-01-25 12:47:31 +08:00
|
|
|
crate::ad7172::SPI_CLOCK,
|
2020-03-12 06:16:48 +08:00
|
|
|
clocks
|
|
|
|
)
|
|
|
|
}
|
|
|
|
|
2020-03-13 02:24:57 +08:00
|
|
|
fn setup_dac0<M1, M2, M3>(
|
|
|
|
clocks: Clocks, spi4: SPI4,
|
|
|
|
sclk: PE2<M1>, sync: PE4<M2>, sdin: PE6<M3>
|
2020-09-07 01:06:59 +08:00
|
|
|
) -> (Dac0Spi, <Channel0 as ChannelPins>::DacSync) {
|
2022-01-25 12:47:31 +08:00
|
|
|
let sclk = sclk.into_alternate();
|
|
|
|
let sdin = sdin.into_alternate();
|
|
|
|
let spi = Spi::new(
|
2020-03-13 02:24:57 +08:00
|
|
|
spi4,
|
2022-01-25 12:47:31 +08:00
|
|
|
(sclk, NoMiso {}, sdin),
|
2020-03-13 04:27:03 +08:00
|
|
|
crate::ad5680::SPI_MODE,
|
2022-01-25 12:47:31 +08:00
|
|
|
crate::ad5680::SPI_CLOCK,
|
2020-03-13 02:24:57 +08:00
|
|
|
clocks
|
|
|
|
);
|
|
|
|
let sync = sync.into_push_pull_output();
|
|
|
|
|
|
|
|
(spi, sync)
|
|
|
|
}
|
|
|
|
|
|
|
|
fn setup_dac1<M1, M2, M3>(
|
|
|
|
clocks: Clocks, spi5: SPI5,
|
|
|
|
sclk: PF7<M1>, sync: PF6<M2>, sdin: PF9<M3>
|
2020-09-07 01:06:59 +08:00
|
|
|
) -> (Dac1Spi, <Channel1 as ChannelPins>::DacSync) {
|
2022-01-25 12:47:31 +08:00
|
|
|
let sclk = sclk.into_alternate();
|
|
|
|
let sdin = sdin.into_alternate();
|
|
|
|
let spi = Spi::new(
|
2020-03-13 02:24:57 +08:00
|
|
|
spi5,
|
2022-01-25 12:47:31 +08:00
|
|
|
(sclk, NoMiso {}, sdin),
|
2020-03-13 04:27:03 +08:00
|
|
|
crate::ad5680::SPI_MODE,
|
2022-01-25 12:47:31 +08:00
|
|
|
crate::ad5680::SPI_CLOCK,
|
2020-03-13 02:24:57 +08:00
|
|
|
clocks
|
|
|
|
);
|
|
|
|
let sync = sync.into_push_pull_output();
|
|
|
|
|
|
|
|
(spi, sync)
|
|
|
|
}
|
2020-03-09 07:27:35 +08:00
|
|
|
}
|
2020-03-13 00:26:14 +08:00
|
|
|
|
|
|
|
pub struct PwmPins {
|
2020-03-20 01:34:57 +08:00
|
|
|
pub max_v0: PwmChannels<TIM3, pwm::C1>,
|
|
|
|
pub max_v1: PwmChannels<TIM3, pwm::C2>,
|
|
|
|
pub max_i_pos0: PwmChannels<TIM1, pwm::C1>,
|
|
|
|
pub max_i_pos1: PwmChannels<TIM1, pwm::C2>,
|
|
|
|
pub max_i_neg0: PwmChannels<TIM1, pwm::C3>,
|
|
|
|
pub max_i_neg1: PwmChannels<TIM1, pwm::C4>,
|
2020-03-13 00:26:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
impl PwmPins {
|
|
|
|
fn setup<M1, M2, M3, M4, M5, M6>(
|
|
|
|
clocks: Clocks,
|
|
|
|
tim1: TIM1,
|
|
|
|
tim3: TIM3,
|
|
|
|
max_v0: PC6<M1>,
|
|
|
|
max_v1: PC7<M2>,
|
|
|
|
max_i_pos0: PE9<M3>,
|
|
|
|
max_i_pos1: PE11<M4>,
|
|
|
|
max_i_neg0: PE13<M5>,
|
|
|
|
max_i_neg1: PE14<M6>,
|
|
|
|
) -> PwmPins {
|
|
|
|
let freq = 20u32.khz();
|
|
|
|
|
2020-09-12 06:35:58 +08:00
|
|
|
fn init_pwm_pin<P: hal::PwmPin<Duty=u16>>(pin: &mut P) {
|
|
|
|
pin.set_duty(0);
|
|
|
|
pin.enable();
|
|
|
|
}
|
2020-03-13 00:26:14 +08:00
|
|
|
let channels = (
|
2022-01-25 12:47:31 +08:00
|
|
|
max_v0.into_alternate(),
|
|
|
|
max_v1.into_alternate(),
|
2020-03-13 00:26:14 +08:00
|
|
|
);
|
2022-01-25 12:47:31 +08:00
|
|
|
//let (mut max_v0, mut max_v1) = pwm::tim3(tim3, channels, clocks, freq);
|
|
|
|
let (mut max_v0, mut max_v1) = Timer::new(tim3, &clocks).pwm(channels, freq);
|
2020-09-12 06:35:58 +08:00
|
|
|
init_pwm_pin(&mut max_v0);
|
|
|
|
init_pwm_pin(&mut max_v1);
|
2020-03-13 00:26:14 +08:00
|
|
|
|
|
|
|
let channels = (
|
2022-01-25 12:47:31 +08:00
|
|
|
max_i_pos0.into_alternate(),
|
|
|
|
max_i_pos1.into_alternate(),
|
|
|
|
max_i_neg0.into_alternate(),
|
|
|
|
max_i_neg1.into_alternate(),
|
2020-03-13 00:26:14 +08:00
|
|
|
);
|
2020-09-12 06:35:58 +08:00
|
|
|
let (mut max_i_pos0, mut max_i_pos1, mut max_i_neg0, mut max_i_neg1) =
|
2022-01-25 12:47:31 +08:00
|
|
|
Timer::new(tim1, &clocks).pwm(channels, freq);
|
2020-09-12 06:35:58 +08:00
|
|
|
init_pwm_pin(&mut max_i_pos0);
|
|
|
|
init_pwm_pin(&mut max_i_neg0);
|
|
|
|
init_pwm_pin(&mut max_i_pos1);
|
|
|
|
init_pwm_pin(&mut max_i_neg1);
|
2020-03-13 00:26:14 +08:00
|
|
|
|
|
|
|
PwmPins {
|
|
|
|
max_v0, max_v1,
|
|
|
|
max_i_pos0, max_i_pos1,
|
|
|
|
max_i_neg0, max_i_neg1,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|