2020-03-12 06:16:48 +08:00
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use core::fmt;
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::blocking::spi::Transfer;
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2020-03-20 05:21:17 +08:00
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use log::info;
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2020-03-12 06:16:48 +08:00
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use super::checksum::{ChecksumMode, Checksum};
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use super::AdcError;
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use super::{
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regs, regs::RegisterData,
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Input, RefSource, PostFilter, DigitalFilterOrder,
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};
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/// AD7172-2 implementation
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///
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/// [Manual](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf)
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pub struct Adc<SPI: Transfer<u8>, NSS: OutputPin> {
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spi: SPI,
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nss: NSS,
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checksum_mode: ChecksumMode,
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}
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impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS> {
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2020-03-12 07:44:15 +08:00
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pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, AdcError<SPI::Error>> {
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2020-03-12 06:16:48 +08:00
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let _ = nss.set_high();
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let mut adc = Adc {
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spi, nss,
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checksum_mode: ChecksumMode::Off,
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};
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adc.reset()?;
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2020-03-12 07:44:15 +08:00
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adc.set_checksum_mode(ChecksumMode::Crc).unwrap();
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2020-03-12 06:16:48 +08:00
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2020-03-12 07:44:15 +08:00
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let mut retries = 0;
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let mut adc_id;
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loop {
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adc_id = adc.identify()?;
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if adc_id & 0xFFF0 == 0x00D0 {
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break;
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} else {
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retries += 1;
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}
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2020-03-12 06:16:48 +08:00
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}
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2020-03-12 07:44:15 +08:00
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info!("ADC id: {:04X} ({} retries)", adc_id, retries);
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2020-03-12 06:16:48 +08:00
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Ok(adc)
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}
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/// `0x00DX` for AD7172-2
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pub fn identify(&mut self) -> Result<u16, AdcError<SPI::Error>> {
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self.read_reg(®s::Id)
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.map(|id| id.id())
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}
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pub fn set_checksum_mode(&mut self, mode: ChecksumMode) -> Result<(), AdcError<SPI::Error>> {
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// Cannot use update_reg() here because checksum_mode is
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// updated between read_reg() and write_reg().
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let mut ifmode = self.read_reg(®s::IfMode)?;
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ifmode.set_crc(mode);
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self.checksum_mode = mode;
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self.write_reg(®s::IfMode, &mut ifmode)?;
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Ok(())
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}
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pub fn set_sync_enable(&mut self, enable: bool) -> Result<(), AdcError<SPI::Error>> {
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self.update_reg(®s::GpioCon, |data| {
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data.set_sync_en(enable);
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})
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}
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pub fn setup_channel(
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&mut self, index: u8, in_pos: Input, in_neg: Input
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) -> Result<(), AdcError<SPI::Error>> {
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self.update_reg(®s::SetupCon { index }, |data| {
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data.set_bipolar(false);
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data.set_refbuf_pos(true);
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data.set_refbuf_neg(true);
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data.set_ainbuf_pos(true);
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data.set_ainbuf_neg(true);
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data.set_ref_sel(RefSource::External);
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})?;
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self.update_reg(®s::FiltCon { index }, |data| {
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data.set_enh_filt_en(true);
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data.set_enh_filt(PostFilter::F16SPS);
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data.set_order(DigitalFilterOrder::Sinc5Sinc1);
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})?;
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// let mut offset = <regs::Offset as regs::Register>::Data::empty();
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// offset.set_offset(0);
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// self.write_reg(®s::Offset { index }, &mut offset);
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self.update_reg(®s::Channel { index }, |data| {
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data.set_setup(index);
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data.set_enabled(true);
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data.set_a_in_pos(in_pos);
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data.set_a_in_neg(in_neg);
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})?;
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Ok(())
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}
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pub fn get_postfilter(&mut self, index: u8) -> Result<Option<PostFilter>, AdcError<SPI::Error>> {
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self.read_reg(®s::FiltCon { index })
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.map(|data| {
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if data.enh_filt_en() {
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Some(data.enh_filt())
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} else {
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None
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}
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})
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}
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pub fn set_postfilter(&mut self, index: u8, filter: Option<PostFilter>) -> Result<(), AdcError<SPI::Error>> {
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self.update_reg(®s::FiltCon { index }, |data| {
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match filter {
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None => data.set_enh_filt_en(false),
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Some(filter) => {
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data.set_enh_filt_en(true);
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data.set_enh_filt(filter);
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}
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}
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})
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}
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/// Returns the channel the data is from
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pub fn data_ready(&mut self) -> Result<Option<u8>, AdcError<SPI::Error>> {
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self.read_reg(®s::Status)
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.map(|status| {
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if status.ready() {
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Some(status.channel())
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} else {
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None
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}
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})
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}
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/// Get data
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2020-03-20 06:39:06 +08:00
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pub fn read_data(&mut self) -> Result<u32, AdcError<SPI::Error>> {
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2020-03-12 06:16:48 +08:00
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self.read_reg(®s::Data)
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.map(|data| data.data())
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}
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fn read_reg<R: regs::Register>(&mut self, reg: &R) -> Result<R::Data, AdcError<SPI::Error>> {
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let mut reg_data = R::Data::empty();
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let address = 0x40 | reg.address();
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let mut checksum = Checksum::new(self.checksum_mode);
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2020-03-12 07:43:11 +08:00
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checksum.feed(&[address]);
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2020-03-12 06:16:48 +08:00
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let checksum_out = checksum.result();
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2020-03-12 07:43:11 +08:00
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2020-03-12 06:16:48 +08:00
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let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
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2020-03-12 07:43:11 +08:00
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checksum.feed(®_data);
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2020-03-12 06:16:48 +08:00
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let checksum_expected = checksum.result();
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if checksum_expected != checksum_in {
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return Err(AdcError::ChecksumMismatch(checksum_expected, checksum_in));
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}
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Ok(reg_data)
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}
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fn write_reg<R: regs::Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), AdcError<SPI::Error>> {
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let address = reg.address();
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let mut checksum = Checksum::new(match self.checksum_mode {
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ChecksumMode::Off => ChecksumMode::Off,
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// write checksums are always crc
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ChecksumMode::Xor => ChecksumMode::Crc,
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ChecksumMode::Crc => ChecksumMode::Crc,
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});
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2020-03-12 07:43:11 +08:00
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checksum.feed(&[address]);
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checksum.feed(®_data);
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2020-03-12 06:16:48 +08:00
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let checksum_out = checksum.result();
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self.transfer(address, reg_data.as_mut(), checksum_out)?;
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Ok(())
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}
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fn update_reg<R, F, A>(&mut self, reg: &R, f: F) -> Result<A, AdcError<SPI::Error>>
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where
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R: regs::Register,
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F: FnOnce(&mut R::Data) -> A,
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{
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let mut reg_data = self.read_reg(reg)?;
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let result = f(&mut reg_data);
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self.write_reg(reg, &mut reg_data)?;
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Ok(result)
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}
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pub fn reset(&mut self) -> Result<(), SPI::Error> {
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let mut buf = [0xFFu8; 8];
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let _ = self.nss.set_low();
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let result = self.spi.transfer(&mut buf);
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let _ = self.nss.set_high();
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result?;
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Ok(())
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}
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fn transfer<'w>(&mut self, addr: u8, reg_data: &'w mut [u8], checksum: Option<u8>) -> Result<Option<u8>, SPI::Error> {
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let mut addr_buf = [addr];
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let _ = self.nss.set_low();
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let result = match self.spi.transfer(&mut addr_buf) {
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Ok(_) => self.spi.transfer(reg_data),
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Err(e) => Err(e),
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};
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let result = match (result, checksum) {
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(Ok(_),None) =>
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Ok(None),
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(Ok(_), Some(checksum_out)) => {
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let mut checksum_buf = [checksum_out; 1];
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match self.spi.transfer(&mut checksum_buf) {
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Ok(_) => Ok(Some(checksum_buf[0])),
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Err(e) => Err(e),
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}
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}
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(Err(e), _) =>
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Err(e),
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};
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let _ = self.nss.set_high();
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result
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}
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}
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