forked from M-Labs/zynq-rs
39 lines
999 B
Rust
39 lines
999 B
Rust
mod regs;
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pub use regs::RegisterBlock;
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pub struct Uart {
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regs: &'static mut RegisterBlock,
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}
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impl Uart {
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pub fn uart0() -> Self {
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let uart_rst_ctrl = super::slcr::UartRstCtrl::new();
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uart_rst_ctrl.reset_uart0();
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// TODO: Route UART 0 RxD/TxD Signals to MIO Pins
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1.
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// d. Disable UART 1 Reference clock, slcr.UART_CLK_CTRL [CLKACT1] bit = 0.
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let uart_clk_ctrl = super::slcr::UartClkCtrl::new();
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uart_clk_ctrl.enable_uart0();
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Uart {
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regs: RegisterBlock::uart0(),
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}.init()
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}
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fn init(self) -> Self {
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self.regs.configure();
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self
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}
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pub fn write_byte(&self, v: u8) {
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unsafe {
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while self.regs.tx_fifo_full() {}
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self.regs.write_byte(v);
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}
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}
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}
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