forked from M-Labs/zynq-rs
253 lines
6.9 KiB
Rust
253 lines
6.9 KiB
Rust
use crate::{register_bit, register_bits};
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use crate::regs::{RegisterR, RegisterW};
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macro_rules! def_reg_r {
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($name:tt, $type: ty, $asm_instr:tt) => {
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impl RegisterR for $name {
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type R = $type;
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#[inline(always)]
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fn read(&self) -> Self::R {
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let mut value: u32;
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unsafe { asm!($asm_instr : "=r" (value) ::: "volatile") }
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value.into()
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}
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}
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}
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}
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macro_rules! def_reg_w {
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($name:ty, $type:ty, $asm_instr:tt) => {
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impl RegisterW for $name {
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type W = $type;
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#[inline(always)]
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fn write(&mut self, value: Self::W) {
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let value: u32 = value.into();
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unsafe { asm!($asm_instr :: "r" (value) :: "volatile") }
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}
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fn zeroed() -> Self::W {
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0u32.into()
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}
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}
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}
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}
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macro_rules! wrap_reg {
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($mod_name: ident) => {
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pub mod $mod_name {
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pub struct Read {
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pub inner: u32,
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}
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impl From<u32> for Read {
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fn from(value: u32) -> Self {
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Read { inner: value }
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}
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}
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pub struct Write {
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pub inner: u32,
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}
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impl From<u32> for Write {
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fn from(value: u32) -> Self {
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Write { inner: value }
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}
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}
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impl Into<u32> for Write {
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fn into(self) -> u32 {
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self.inner
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}
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}
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}
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}
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}
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/// Stack Pointer
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pub struct SP;
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def_reg_r!(SP, u32, "mov $0, sp");
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def_reg_w!(SP, u32, "mov sp, $0");
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/// Link register (function call return address)
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pub struct LR;
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def_reg_r!(LR, u32, "mov $0, lr");
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def_reg_w!(LR, u32, "mov lr, $0");
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pub struct MPIDR;
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def_reg_r!(MPIDR, u32, "mrc p15, 0, $0, c0, c0, 5");
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pub struct DFAR;
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def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");
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pub struct DFSR;
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def_reg_r!(DFSR, u32, "mrc p15, 0, $0, c5, c0, 0");
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pub struct SCTLR;
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wrap_reg!(sctlr);
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def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, $0, c1, c0, 0");
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def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, $0, c1, c0, 0");
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register_bit!(sctlr,
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/// Enables MMU
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m, 0);
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register_bit!(sctlr,
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/// Strict Alignment Checking
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a, 1);
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register_bit!(sctlr,
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/// Data Caching
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c, 2);
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register_bit!(sctlr, sw, 10);
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register_bit!(sctlr, z, 11);
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register_bit!(sctlr, i, 12);
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register_bit!(sctlr, v, 13);
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register_bit!(sctlr, ha, 17);
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register_bit!(sctlr, ee, 25);
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register_bit!(sctlr,
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/// (read-only)
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nmfi, 27);
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register_bit!(sctlr, unaligned, 22);
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register_bit!(sctlr,
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/// TEX Remap Enable
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tre, 28);
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register_bit!(sctlr,
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/// Access Flag Enable
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afe, 29);
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register_bit!(sctlr,
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/// Thumb Exception Enable
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te, 30);
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impl crate::regs::RegisterRW for SCTLR {
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fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
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// todo: this may fail for .nmfi and, in non-secure state,
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// also RR (bit 14)
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let inner = self.read().inner;
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let inner_w = f(
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sctlr::Read { inner },
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sctlr::Write { inner }
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);
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self.write(inner_w);
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}
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}
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/// Auxiliary Control Register
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pub struct ACTLR;
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wrap_reg!(actlr);
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def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, $0, c1, c0, 1");
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def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, $0, c1, c0, 1");
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// SMP bit
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register_bit!(actlr, parity_on, 9);
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register_bit!(actlr, alloc_one_way, 8);
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register_bit!(actlr, excl, 7);
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register_bit!(actlr, smp, 6);
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register_bit!(actlr, write_full_line_of_zeros, 3);
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register_bit!(actlr, l1_prefetch_enable, 2);
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// Cache/TLB maintenance broadcast
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register_bit!(actlr, fw, 0);
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impl crate::regs::RegisterRW for ACTLR {
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fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
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let inner = self.read().inner;
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let inner_w = f(
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actlr::Read { inner },
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actlr::Write { inner }
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);
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self.write(inner_w);
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}
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}
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/// Domain Access Control Register
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pub struct DACR;
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def_reg_r!(DACR, u32, "mrc p15, 0, $0, c3, c0, 0");
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def_reg_w!(DACR, u32, "mcr p15, 0, $0, c3, c0, 0");
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/// Translation Table Base Register 0
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pub struct TTBR0;
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/// Translation Table Base Register 1
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pub struct TTBR1;
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def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, $0, c2, c0, 0");
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def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, $0, c2, c0, 0");
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def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, $0, c2, c0, 1");
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def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, $0, c2, c0, 1");
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wrap_reg!(ttbr);
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register_bits!(ttbr, table_base, u32, 14, 31);
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register_bit!(ttbr, irgn0, 6);
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register_bits!(ttbr, rgn, u8, 3, 4);
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register_bit!(ttbr,
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/// Translation table walk to shared memory?
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s, 1);
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register_bit!(ttbr, irgn1, 0);
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/// Invalidate TLBs
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#[inline(always)]
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pub fn tlbiall() {
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unsafe {
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asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate I-Cache
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#[inline(always)]
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pub fn iciallu() {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate Branch Predictor Array
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#[inline(always)]
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pub fn bpiall() {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate D-Cache
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#[inline(always)]
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pub fn dcisw(setway: u32) {
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// TODO: $0 is r11 at what value?
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unsafe {
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// steinb: the following is incorrect
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//asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
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// acc. to ARM Architecture Reference Manual, Figure B3-32;
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// also see example code (for DCCISW, but DCISW will be
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// analogous) "Example code for cache maintenance operations"
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// on pages B2-1286 and B2-1287.
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asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
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}
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}
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/// A made-up "instruction": invalidate all of the L1 D-Cache
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#[inline(always)]
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pub fn dciall() {
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// the cache associativity could be read from a register, but will
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// always be 4 in L1 data cache of a cortex a9
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let ways = 4;
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let bit_pos_of_way = 30; // 32 - log2(ways)
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// the cache sets could be read from a register, but are always
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// 256 for the cores in the zync-7000; in general, 128 or 512 are
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// also possible for a Cortex-A9.
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let sets = 256;
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let bit_pos_of_set = 5; // for a line size of 8 words = 2^5 bytes
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// select L1 data cache
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unsafe {
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asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
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}
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// Invalidate entire D-Cache by iterating every set and every way
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for set in 0..sets {
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for way in 0..ways {
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dcisw((set << bit_pos_of_set) | (way << bit_pos_of_way));
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}
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}
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}
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/// clear cache line by virtual address to point of coherency (DCCMVAC)
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#[inline]
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pub fn dccmvac(addr: u32) {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
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}
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}
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