forked from M-Labs/zynq-rs
141 lines
3.3 KiB
Rust
141 lines
3.3 KiB
Rust
pub mod id;
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use id::{identify_phy, PhyIdentifier};
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mod status;
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pub use status::Status;
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mod control;
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pub use control::Control;
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mod pssr;
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pub use pssr::PSSR;
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#[derive(Clone, Debug, PartialEq)]
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pub struct Link {
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pub speed: LinkSpeed,
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pub duplex: LinkDuplex,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum LinkSpeed {
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S10,
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S100,
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S1000,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum LinkDuplex {
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Half,
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Full,
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}
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pub trait PhyAccess {
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fn read_phy(&mut self, addr: u8, reg: u8) -> u16;
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fn write_phy(&mut self, addr: u8, reg: u8, data: u16);
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}
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#[derive(Clone)]
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pub struct Phy {
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pub addr: u8,
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device: PhyDevice,
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}
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#[derive(Clone, Copy)]
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pub enum PhyDevice {
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Marvell88E1116R,
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Rtl8211E,
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}
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const OUI_MARVELL: u32 = 0x005043;
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const OUI_REALTEK: u32 = 0x000732;
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impl Phy {
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/// Probe all addresses on MDIO for a known PHY
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pub fn find<PA: PhyAccess>(pa: &mut PA) -> Option<Phy> {
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(1..32).filter_map(|addr| {
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match identify_phy(pa, addr) {
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Some(PhyIdentifier {
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oui: OUI_MARVELL,
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model: 36,
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..
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}) => Some(PhyDevice::Marvell88E1116R),
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Some(PhyIdentifier {
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oui: OUI_REALTEK,
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model: 0b010001,
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rev: 0b0101,
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}) => Some(PhyDevice::Rtl8211E),
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_ => None,
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}.map(|device| Phy { addr, device })
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}).next()
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}
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pub fn name(&self) -> &'static str {
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match self.device {
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PhyDevice::Marvell88E1116R => &"Marvell 88E1116R",
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PhyDevice::Rtl8211E => &"RTL8211E",
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}
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}
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pub fn read_reg<PA, PR>(&self, pa: &mut PA) -> PR
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where
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PA: PhyAccess,
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PR: PhyRegister + From<u16>,
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{
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pa.read_phy(self.addr, PR::addr()).into()
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}
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pub fn modify_reg<PA, PR, F>(&self, pa: &mut PA, mut f: F)
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where
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PA: PhyAccess,
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PR: PhyRegister + From<u16> + Into<u16>,
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F: FnMut(PR) -> PR,
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{
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let reg = pa.read_phy(self.addr, PR::addr()).into();
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let reg = f(reg);
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pa.write_phy(self.addr, PR::addr(), reg.into())
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}
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pub fn modify_control<PA, F>(&self, pa: &mut PA, f: F)
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where
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PA: PhyAccess,
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F: FnMut(Control) -> Control,
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{
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self.modify_reg(pa, f)
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}
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pub fn get_control<PA: PhyAccess>(&self, pa: &mut PA) -> Control {
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self.read_reg(pa)
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}
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pub fn get_status<PA: PhyAccess>(&self, pa: &mut PA) -> Status {
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self.read_reg(pa)
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}
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pub fn get_link<PA: PhyAccess>(&self, pa: &mut PA) -> Option<Link> {
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let status = self.get_status(pa);
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if !status.link_status() {
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None
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} else if status.cap_1000base_t_extended_status() {
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let phy_status: PSSR = self.read_reg(pa);
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phy_status.get_link()
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} else {
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status.get_link()
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}
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}
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pub fn reset<PA: PhyAccess>(&self, pa: &mut PA) {
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self.modify_control(pa, |control|
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control.set_reset(true)
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);
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while self.get_control(pa).reset() {}
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}
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pub fn restart_autoneg<PA: PhyAccess>(&self, pa: &mut PA) {
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self.modify_control(pa, |control|
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control.set_autoneg_enable(true)
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.set_restart_autoneg(true)
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);
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}
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}
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pub trait PhyRegister {
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fn addr() -> u8;
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}
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