forked from M-Labs/zynq-rs
75 lines
2.2 KiB
Rust
75 lines
2.2 KiB
Rust
//! ARM Generic Interrupt Controller
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use bit_field::BitField;
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use libregister::{RegisterW, RegisterRW};
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use super::mpcore;
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#[derive(Debug, Clone, Copy)]
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pub struct InterruptId(u8);
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#[derive(Debug, Clone, Copy)]
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pub enum InterruptSensitivity {
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Level,
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Edge,
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}
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pub struct InterruptController {
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mpcore: mpcore::RegisterBlock,
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}
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impl InterruptController {
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pub fn new(mpcore: mpcore::RegisterBlock) -> Self {
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InterruptController { mpcore }
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}
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pub fn disable_interrupts(&mut self) {
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self.mpcore.iccicr.modify(|_, w| w.enable_ns(false)
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.enable_s(false));
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self.mpcore.icddcr.modify(|_, w| w.enable_secure(false)
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.enable_non_secure(false));
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}
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/// enable interrupt signaling
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pub fn enable_interrupts(&mut self) {
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self.mpcore.iccicr.modify(|_, w| w.enable_ns(true)
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.enable_s(true));
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self.mpcore.icddcr.modify(|_, w| w.enable_secure(true));
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}
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pub fn enable(&mut self, id: InterruptId, target_cpu: u32, sensitivity: InterruptSensitivity) {
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assert!(target_cpu < 2);
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self.disable_interrupts();
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// enable
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let m = (id.0 >> 5) as usize;
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let n = (id.0 & 0x1F) as usize;
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assert!(m < 3);
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unsafe {
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self.mpcore.icdiser[m].modify(|mut icdiser| *icdiser.set_bit(n, true));
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}
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// target cpu
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let m = (id.0 >> 2) as usize;
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let n = (8 * (id.0 & 3)) as usize;
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unsafe {
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self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu + 1));
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}
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// sensitivity
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let m = (id.0 >> 4) as usize;
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let n = (2 * (id.0 & 0xF)) as usize;
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unsafe {
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self.mpcore.icdicfr[m].modify(|mut icdicfr| *icdicfr.set_bits(n..=n+1, match sensitivity {
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InterruptSensitivity::Level => 0b00,
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InterruptSensitivity::Edge => 0b10,
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}));
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}
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// filter no interrupts (lowest priority)
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self.mpcore.iccpmr.write(mpcore::ICCPMR::zeroed().priority(0xFF));
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self.enable_interrupts();
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}
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}
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