use core::fmt; use libregister::*; mod regs; use crate::println; pub struct DevC { regs: &'static mut regs::RegisterBlock, } impl DevC { pub fn new() -> Self { DevC { regs: regs::RegisterBlock::devc(), } } pub fn enable_and_select_pcap(&mut self) { self.regs.control.modify(|_, w| { w.pcap_mode(true) .pcap_pr(true) }); let status = self.regs.control.read(); println!("pcap mode: {}, pcap_pr: {}",status.pcap_pr(), status.pcap_mode()); } pub fn enable_and_select_icap(&mut self) { self.regs.control.modify(|_, w| { w.pcap_mode(true) .pcap_pr(false) }) } pub fn clear_interrupts(&mut self) { self.regs.int_sts.modify(|_, w| { w.pps_gts_usr_b_int(true) .pps_fst_cfg_b_int(true) .pps_gpwrdwn_b_int(true) .pps_gts_cfg_b_int(true) .pps_cfg_reset_b_int(true) .ixr_axi_wto(true) .ixr_axi_werr(true) .ixr_axi_rto(true) .ixr_axi_rerr(true) .ixr_rx_fifo_ov(true) .ixr_wr_fifo_lvl(true) .ixr_rd_fifo_lvl(true) .ixr_dma_cmd_err(true) .ixr_dma_q_ov(true) .ixr_dma_done(true) .ixr_d_p_done(true) .ixr_p2d_len_err(true) .ixr_pcfg_hmac_err(true) .ixr_pcfg_seu_err(true) .ixr_pcfg_por_b(true) .ixr_pcfg_cfg_rst(true) .ixr_pcfg_done(true) .ixr_pcfg_init_pe(true) .ixr_pcfg_init_ne(true) }) } pub fn initialize_pl(&mut self) { self.regs.control.modify(|_, w| { w.pcfg_prog_b(true) }); let control = self.regs.control.read(); println!("pcfg_prog_b mode: {}",control.pcfg_prog_b()); self.regs.control.modify(|_, w| { w.pcfg_prog_b(false) }); let control = self.regs.control.read(); println!("pcfg_prog_b mode: {}",control.pcfg_prog_b()); self.wait_for_status_pcfg_init_to_be(false); self.regs.control.modify(|_, w| { w.pcfg_prog_b(true) }); let control = self.regs.control.read(); println!("pcfg_prog_b mode: {}",control.pcfg_prog_b()); self.regs.int_sts.modify(|_,w| { w.ixr_pcfg_done(true) }); let int_sts= self.regs.int_sts.read(); println!("ixr_pcfg_done mode: {}",int_sts.ixr_pcfg_done()); } pub fn wait_for_pl_to_be_ready(&self) { self.wait_for_status_pcfg_init_to_be(true) } pub fn disable_pcap_loopback(&mut self) { let mctrl = self.regs.mctrl.read(); println!("mctrl pcap_lpbk: {}", mctrl.pcap_lpbk()); self.regs.mctrl.modify(|_,w| { w.pcap_lpbk(false) }); let mctrl = self.regs.mctrl.read(); println!("mctrl pcap_lpbk: {}", mctrl.pcap_lpbk()); } pub fn enable_pcap_secure_mode(&mut self) { self.regs.control.modify(|_, w| { w.pcap_rate_en(true) }); } pub fn disable_pcap_secure_mode(&mut self) { let control = self.regs.control.read(); println!("control pcap_rate_en: {}", control.pcap_rate_en()); self.regs.control.modify(|_, w| { w.pcap_rate_en(false) }); let control = self.regs.control.read(); println!("control pcap_rate_en: {}", control.pcap_rate_en()); } pub fn wait_for_dma_transfer(&self) { self.wait_for_int_sts_ixr_dma_done_to_be(true); } pub fn load_dma(&mut self) { self.regs.dma_src_addr.modify(|_, w| { w.src_addr(regs::SRC_ADDR) }); self.regs.dma_dest_addr.modify(|_, w| { w.dest_addr(regs::DEST_ADDR) }); } fn wait_for_status_pcfg_init_to_be(&self, value: bool) { loop { let status = self.regs.status.read(); println!("expected value for pcfg_init: {}, actual: {}",value, status.pcfg_init()); if value == status.pcfg_init() { return } } } fn wait_for_int_sts_ixr_dma_done_to_be(&self, value: bool) { loop { let int_sts = self.regs.int_sts.read(); println!("expected value for int_sts.ixr_dma_done: {}, actual: {}",value, int_sts.ixr_dma_done()); if value == int_sts.ixr_dma_done() { return } } } }