use volatile_register::{RO, WO, RW}; use crate::{register, register_bit, register_bits, regs::*}; #[repr(C)] pub struct RegisterBlock { pub net_ctrl: NetCtrl, pub net_cfg: NetCfg, pub net_status: RO, pub unused0: RO, pub dma_cfg: RW, pub tx_status: TxStatus, pub rx_qbar: RxQbar, pub tx_qbar: TxQbar, pub rx_status: RxStatus, pub intr_status: RW, pub intr_en: WO, pub intr_dis: IntrDis, pub intr_mask: RW, pub phy_maint: RW, pub rx_pauseq: RO, pub tx_pauseq: RW, pub unused1: [RO; 16], pub hash_bot: RW, pub hash_top: RW, pub spec_addr1_bot: RW, pub spec_addr1_top: RW, pub spec_addr2_bot: RW, pub spec_addr2_top: RW, pub spec_addr3_bot: RW, pub spec_addr3_top: RW, pub spec_addr4_bot: RW, pub spec_addr4_top: RW, pub type_id_match1: RW, pub type_id_match2: RW, pub type_id_match3: RW, pub type_id_match4: RW, pub wake_on_lan: RW, pub ipg_stretch: RW, pub stacked_vlan: RW, pub tx_pfc_pause: RW, pub spec_addr1_mask_bot: RW, pub spec_addr1_mask_top: RW, pub unused2: [RO; 11], pub module_id: RO, pub octets_tx_bot: RO, pub octets_tx_top: RO, pub frames_tx: RO, pub broadcast_frames_tx: RO, pub multi_frames_tx: RO, pub pause_frames_tx: RO, pub frames_64b_tx: RO, pub frames_65to127b_tx: RO, pub frames_128to255b_tx: RO, pub frames_256to511b_tx: RO, pub frames_512to1023b_tx: RO, pub frames_1024to1518b_tx: RO, pub tx_under_runs: RO, pub unused3: RO, pub single_collisn_frames: RO, pub multi_collisn_frames: RO, pub excessive_collisns: RO, pub late_collisns: RO, pub deferred_tx_frames: RO, pub carrier_sense_errs: RO, pub octets_rx_bot: RO, pub octets_rx_top: RO, pub frames_rx: RO, pub bdcast_fames_rx: RO, pub multi_frames_rx: RO, pub pause_rx: RO, pub frames_64b_rx: RO, pub frames_65to127b_rx: RO, pub frames_128to255b_rx: RO, pub frames_256to511b_rx: RO, pub frames_512to1023b_rx: RO, pub frames_1024to1518b_rx: RO, pub unused4: RO, pub undersz_rx: RO, pub oversz_rx: RO, pub jab_rx: RO, pub fcs_errors: RO, pub length_field_errors: RO, pub rx_symbol_errors: RO, pub align_errors: RO, pub rx_resource_errors: RO, pub rx_overrun_errors: RO, pub ip_hdr_csum_errors: RO, pub tcp_csum_errors: RO, pub udp_csum_errors: RO, pub unused5: [RO; 5], pub timer_strobe_s: RW, pub timer_strobe_ns: RW, pub timer_s: RW, pub timer_ns: RW, pub timer_adjust: RW, pub timer_incr: RW, pub ptp_tx_s: RO, pub ptp_tx_ns: RO, pub ptp_rx_s: RO, pub ptp_rx_ns: RO, pub ptp_peer_tx_s: RO, pub ptp_peer_tx_ns: RO, pub ptp_peer_rx_s: RO, pub ptp_peer_rx_ns: RO, pub unused6: [RO; 33], pub design_cfg2: RO, pub design_cfg3: RO, pub design_cfg4: RO, pub design_cfg5: RO, } impl RegisterBlock { const GEM0: *mut Self = 0xE000B000 as *mut _; const GEM1: *mut Self = 0xE000C000 as *mut _; pub fn gem0() -> &'static mut Self { unsafe { &mut *Self::GEM0 } } pub fn gem1() -> &'static mut Self { unsafe { &mut *Self::GEM1 } } } register!(net_ctrl, NetCtrl, RW, u32); register_bit!(net_ctrl, clear_stat_regs, 5); register!(net_cfg, NetCfg, RW, u32); /// false for 10Mbps, true for 100Mbps register_bit!(net_cfg, speed, 0); register_bit!(net_cfg, full_duplex, 1); /// Discard non-VLAN frames register_bit!(net_cfg, disc_non_vlan, 2); /// Accept all valid frames? register_bit!(net_cfg, copy_all, 4); /// Don't accept broadcast destination address register_bit!(net_cfg, no_broadcast, 5); /// Multicast hash enable register_bit!(net_cfg, multi_hash_en, 6); /// Unicast hash enable register_bit!(net_cfg, uni_hash_en, 7); /// Accept frames up to 1536 bytes (instead of up to 1518 bytes) register_bit!(net_cfg, rx_1536_byte_frames, 8); /// External address match enable - when set the external address /// match interface can be used to copy frames to memory. register_bit!(net_cfg, ext_addr_match_en, 9); /// Gigabit mode enable register_bit!(net_cfg, gige_en, 10); /// Enable TBI instead of GMII/MII interface? register_bit!(net_cfg, pcs_sel, 11); /// Retry test (reduces backoff between collisions to one slot) register_bit!(net_cfg, retry_test, 12); /// Pause frame enable register_bit!(net_cfg, pause_en, 13); /// Receive buffer offset register_bits!(net_cfg, rx_buf_offset, u8, 14, 15); /// Length field error frame discard register_bit!(net_cfg, len_err_frame_disc, 16); /// Write received frames to memory with Frame Check Sequence removed register_bit!(net_cfg, fcs_remove, 17); /// MDC clock divison register_bits!(net_cfg, mdc_clk_div, u8, 18, 20); /// Data bus width register_bits!(net_cfg, dbus_width, u8, 21, 22); /// Disable copy of pause frames register_bit!(net_cfg, dis_cp_pause_frame, 23); /// Receive checksum offload enable register_bit!(net_cfg, rx_chksum_offld_en, 24); /// Enable frames to be received in half-duplex mode while /// transmitting register_bit!(net_cfg, rx_hd_while_tx, 25); /// Ignore Rx Framce Check Sequence (errors will not be rejected) register_bit!(net_cfg, ignore_rx_fcs, 26); /// SGMII mode enable register_bit!(net_cfg, sgmii_en, 27); /// IPG stretch enable register_bit!(net_cfg, ipg_stretch_en, 28); /// Receive bad preamble register_bit!(net_cfg, rx_bad_preamble, 29); /// Ignore IPG rx_er register_bit!(net_cfg, ignore_ipg_rx_er, 30); /// NA register_bit!(net_cfg, unidir_en, 31); register!(tx_status, TxStatus, RW, u32); register_bit!(tx_status, used_bit_read, 0); register_bit!(tx_status, collision, 1); register_bit!(tx_status, retry_limit_exceeded, 2); register_bit!(tx_status, tx_go, 3); register_bit!(tx_status, tx_corr_ahb_err, 4); register_bit!(tx_status, tx_complete, 5); register_bit!(tx_status, tx_under_run, 6); register_bit!(tx_status, late_collision, 7); register_bit!(tx_status, hresp_not_ok, 8); register!(rx_status, RxStatus, RW, u32); register_bit!(rx_status, buffer_not_avail, 0); register_bit!(rx_status, frame_recd, 1); register_bit!(rx_status, rx_overrun, 2); register_bit!(rx_status, hresp_not_ok, 3); register!(rx_qbar, RxQbar, RW, u32); register_bits!(rx_qbar, rx_q_baseaddr, u32, 2, 31); register!(tx_qbar, TxQbar, RW, u32); register_bits!(tx_qbar, tx_q_baseaddr, u32, 2, 31); register!(intr_dis, IntrDis, WO, u32); register_bit!(intr_dis, mgmt_done, 0); register_bit!(intr_dis, rx_complete, 1); register_bit!(intr_dis, rx_used_read, 2); register_bit!(intr_dis, tx_used_read, 3); register_bit!(intr_dis, tx_underrun, 4); register_bit!(intr_dis, retry_ex_late_collisn, 5); register_bit!(intr_dis, tx_corrupt_ahb_err, 6); register_bit!(intr_dis, tx_complete, 7); register_bit!(intr_dis, link_chng, 9); register_bit!(intr_dis, rx_overrun, 10); register_bit!(intr_dis, hresp_not_ok, 11); register_bit!(intr_dis, pause_nonzeroq, 12); register_bit!(intr_dis, pause_zero, 13); register_bit!(intr_dis, pause_tx, 14); register_bit!(intr_dis, ex_intr, 15); register_bit!(intr_dis, autoneg_complete, 16); register_bit!(intr_dis, partner_pg_rx, 17); register_bit!(intr_dis, delay_req_rx, 18); register_bit!(intr_dis, sync_rx, 19); register_bit!(intr_dis, delay_req_tx, 20); register_bit!(intr_dis, sync_tx, 21); register_bit!(intr_dis, pdelay_req_rx, 22); register_bit!(intr_dis, pdelay_resp_rx, 23); register_bit!(intr_dis, pdelay_req_tx, 24); register_bit!(intr_dis, pdelay_resp_tx, 25); register_bit!(intr_dis, tsu_sec_incr, 26);