From fdc6c38de64f27463f8bf6a57dae766691822351 Mon Sep 17 00:00:00 2001 From: Astro Date: Tue, 7 May 2019 00:01:43 +0200 Subject: [PATCH] enable_uart0(): add srcsel --- src/slcr.rs | 15 +++++++++++++-- src/uart/mod.rs | 4 ---- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/slcr.rs b/src/slcr.rs index cc31b14..7919998 100644 --- a/src/slcr.rs +++ b/src/slcr.rs @@ -2,10 +2,17 @@ use volatile_register::{RO, WO, RW}; use crate::{register, register_bit, register_bits, regs::Register}; +pub enum PllSource { + IoPll = 0b00, + ArmPll = 0b10, + DdrPll = 0b11, +} + register!(uart_clk_ctrl, UartClkCtrl, u32); register_bit!(uart_clk_ctrl, clkact0, 0); register_bit!(uart_clk_ctrl, clkact1, 1); register_bits!(uart_clk_ctrl, divisor, u8, 8, 13); +register_bits!(uart_clk_ctrl, srcsel, u8, 4, 5); impl UartClkCtrl { const ADDR: *mut Self = 0xF8000154 as *mut _; @@ -15,8 +22,12 @@ impl UartClkCtrl { pub fn enable_uart0(&self) { self.modify(|_, w| { - w.clkact0(true) - .divisor(0x14) + // a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14. + // b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0. + // c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1. + w.divisor(0x14) + .srcsel(PllSource::IoPll as u8) + .clkact0(true) }) } } diff --git a/src/uart/mod.rs b/src/uart/mod.rs index 77ba127..1221b4d 100644 --- a/src/uart/mod.rs +++ b/src/uart/mod.rs @@ -11,10 +11,6 @@ impl Uart { uart_rst_ctrl.reset_uart0(); // TODO: Route UART 0 RxD/TxD Signals to MIO Pins - // a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14. - // b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0. - // c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1. - // d. Disable UART 1 Reference clock, slcr.UART_CLK_CTRL [CLKACT1] bit = 0. let uart_clk_ctrl = super::slcr::UartClkCtrl::new(); uart_clk_ctrl.enable_uart0();