From c0610ad66a2aa38db0bf896bece0103ad8b5c239 Mon Sep 17 00:00:00 2001 From: Astro Date: Thu, 30 May 2019 02:26:19 +0200 Subject: [PATCH] slcr: init gem* rclk/clk --- src/eth/mod.rs | 14 ++++++++++++++ src/slcr.rs | 26 ++++++++++++++++++++++---- 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/src/eth/mod.rs b/src/eth/mod.rs index aa1bb7f..fa859ae 100644 --- a/src/eth/mod.rs +++ b/src/eth/mod.rs @@ -119,6 +119,20 @@ impl Eth { } pub fn gem0() -> Self { + slcr::RegisterBlock::unlocked(|slcr| { + // Enable gem0 ref clock + slcr.gem0_rclk_ctrl.write( + slcr::RclkCtrl::zeroed() + .clkact(true) + ); + slcr.gem0_clk_ctrl.write( + slcr::ClkCtrl::zeroed() + .clkact(true) + .srcsel(slcr::PllSource::IoPll) + .divisor(10) + ); + }); + let regs = regs::RegisterBlock::gem0(); Eth { regs }.init() } diff --git a/src/slcr.rs b/src/slcr.rs index 9ebd38a..e88e6d3 100644 --- a/src/slcr.rs +++ b/src/slcr.rs @@ -33,10 +33,10 @@ pub struct RegisterBlock { pub aper_clk_ctrl: AperClkCtrl, pub usb0_clk_ctrl: RW, pub usb1_clk_ctrl: RW, - pub gem0_rclk_ctrl: RW, - pub gem1_rclk_ctrl: RW, - pub gem0_clk_ctrl: RW, - pub gem1_clk_ctrl: RW, + pub gem0_rclk_ctrl: RclkCtrl, + pub gem1_rclk_ctrl: RclkCtrl, + pub gem0_clk_ctrl: ClkCtrl, + pub gem1_clk_ctrl: ClkCtrl, pub smc_clk_ctrl: RW, pub lqspi_clk_ctrl: RW, pub sdio_clk_ctrl: RW, @@ -254,6 +254,24 @@ impl AperClkCtrl { } } +register!(rclk_ctrl, RclkCtrl, RW, u32); +register_bit!(rclk_ctrl, + /// Ethernet controller Rx clock control + clkact, 0); +register_bit!(rclk_ctrl, + /// false: MIO, true: EMIO + srcsel, 4); + +register!(clk_ctrl, ClkCtrl, RW, u32); +register_bits!(clk_ctrl, + /// Divisor for source clock + divisor, u8, 8, 13); +register_bits_typed!(clk_ctrl, + /// Source to generate the ref clock + srcsel, u8, PllSource, 4, 5); +register_bit!(clk_ctrl, + /// SMC reference clock control + clkact, 0); register!(uart_clk_ctrl, UartClkCtrl, RW, u32); register_bit!(uart_clk_ctrl, clkact0, 0);