From a36a82d86de88ee730ba5aae72895c40bc85711c Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 4 Aug 2020 22:15:01 +0800
Subject: [PATCH] reduce ethernet verbosity

---
 libboard_zynq/src/eth/mod.rs | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/libboard_zynq/src/eth/mod.rs b/libboard_zynq/src/eth/mod.rs
index 5bd49c3..46f1b3a 100644
--- a/libboard_zynq/src/eth/mod.rs
+++ b/libboard_zynq/src/eth/mod.rs
@@ -2,7 +2,7 @@ use core::{
     marker::PhantomData,
     ops::{Deref, DerefMut},
 };
-use log::{error, info, warn};
+use log::{debug, info, warn, error};
 use libregister::*;
 use super::slcr;
 use super::clocks::Clocks;
@@ -132,10 +132,10 @@ fn calculate_tx_divisors(tx_clock: u32) -> (u8, u8) {
         }
     }
     let result = best.unwrap();
-    info!("Eth TX clock for {}: {} / {} / {} = {}",
-          tx_clock, io_pll,
-          result.0, result.1,
-          io_pll / result.0 as u32 / result.1 as u32
+    debug!("Eth TX clock for {}: {} / {} / {} = {}",
+           tx_clock, io_pll,
+           result.0, result.1,
+           io_pll / result.0 as u32 / result.1 as u32
     );
     result
 }