libboard_zynq: work around Kasli-SoC MDIO breakage (#78)

libboard_zynq/src/eth/phy/mod.rs

@@ -1,5 +1,4 @@
 pub mod id;
-use id::{identify_phy, PhyIdentifier};
 mod status;
 pub use status::Status;
 mod control;
@@ -31,16 +30,25 @@ pub trait PhyAccess {
     fn write_phy(&mut self, addr: u8, reg: u8, data: u16);
 }
 
-#[derive(Clone)]
+pub trait PhyRegister {
-pub struct Phy {
+    fn addr() -> u8;
-    pub addr: u8,
 }
 
-const OUI_MARVELL: u32 = 0x005043;
+#[cfg(not(feature = "target_kasli_soc"))]
-const OUI_REALTEK: u32 = 0x000732;
+mod phy_impl {
-const OUI_LANTIQ : u32 = 0x355969;
+    use super::*;
+    use id::{identify_phy, PhyIdentifier};
 
-impl Phy {
+    #[derive(Clone)]
+    pub struct Phy {
+        pub addr: u8,
+    }
+
+    const OUI_MARVELL: u32 = 0x005043;
+    const OUI_REALTEK: u32 = 0x000732;
+    const OUI_LANTIQ : u32 = 0x355969;
+
+    impl Phy {
         /// Probe all addresses on MDIO for a known PHY
         pub fn find<PA: PhyAccess>(pa: &mut PA) -> Option<Phy> {
             (1..32).find(|addr| {
@@ -134,8 +142,42 @@ impl Phy {
                     .set_restart_autoneg(true)
             );
         }
+    }
 }
 
-pub trait PhyRegister {
+#[cfg(feature = "target_kasli_soc")]
-    fn addr() -> u8;
+mod phy_impl {
+    use super::*;
+
+    #[derive(Clone)]
+    pub struct Phy {
+    }
+
+    impl Phy {
+        pub fn find<PA: PhyAccess>(_pa: &mut PA) -> Option<Phy> {
+            Some(Phy {})
+        }
+
+        pub fn get_link<PA: PhyAccess>(&self, _pa: &mut PA) -> Option<Link> {
+            Some(Link {
+                speed: LinkSpeed::S1000,
+                duplex: LinkDuplex::Full,
+            })
+        }
+
+        pub fn modify_control<PA, F>(&self, _pa: &mut PA, _f: F)
+        where
+            PA: PhyAccess,
+            F: FnMut(Control) -> Control,
+        {
+        }
+
+        pub fn reset<PA: PhyAccess>(&self, _pa: &mut PA) {
+        }
+
+        pub fn restart_autoneg<PA: PhyAccess>(&self, _pa: &mut PA) {
+        }
+    }
 }
+
+pub use phy_impl::*;