From 8a98cef3fc0040201f8baf518ec8d1237e0e56fa Mon Sep 17 00:00:00 2001 From: Astro Date: Fri, 3 Apr 2020 00:17:25 +0200 Subject: [PATCH] libboard_zynq: fix some hw setup --- libboard_zynq/src/ddr/mod.rs | 16 ++++++++++------ libboard_zynq/src/ddr/regs.rs | 1 + libboard_zynq/src/flash/mod.rs | 7 ++++++- libboard_zynq/src/slcr.rs | 2 +- 4 files changed, 18 insertions(+), 8 deletions(-) diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs index ce74e4a..b9d99e6 100644 --- a/libboard_zynq/src/ddr/mod.rs +++ b/libboard_zynq/src/ddr/mod.rs @@ -1,6 +1,6 @@ use libregister::{RegisterR, RegisterW, RegisterRW}; use crate::{print, println}; -use super::slcr; +use super::slcr::{self, DdriobVrefSel}; use super::clocks::{Clocks, source::{DdrPll, ClockSource}}; mod regs; @@ -174,21 +174,25 @@ impl DdrRam { ); #[cfg(feature = "target_zc706")] slcr.ddriob_ddr_ctrl.modify(|_, w| w - .vref_ext_en_lower(true) - .vref_ext_en_upper(true) + .vref_int_en(true) + .vref_sel(DdriobVrefSel::Vref0_75V) + .vref_ext_en_lower(false) + .vref_ext_en_upper(false) ); }); } /// Reset DDR controller fn reset_ddrc(&mut self) { - self.regs.ddrc_ctrl.modify(|_, w| w - .soft_rstb(false) - ); #[cfg(feature = "target_zc706")] let width = regs::DataBusWidth::Width32bit; #[cfg(feature = "target_cora_z7_10")] let width = regs::DataBusWidth::Width16bit; + self.regs.ddrc_ctrl.modify(|_, w| w + .soft_rstb(false) + .powerdown_en(false) + .data_bus_width(width) + ); self.regs.ddrc_ctrl.modify(|_, w| w .soft_rstb(true) .powerdown_en(false) diff --git a/libboard_zynq/src/ddr/regs.rs b/libboard_zynq/src/ddr/regs.rs index 1ca54fc..c72842e 100644 --- a/libboard_zynq/src/ddr/regs.rs +++ b/libboard_zynq/src/ddr/regs.rs @@ -3,6 +3,7 @@ use volatile_register::{RO, RW}; use libregister::{register, register_bit, register_bits_typed}; #[allow(unused)] +#[derive(Clone, Copy)] #[repr(u8)] pub enum DataBusWidth { Width32bit = 0b00, diff --git a/libboard_zynq/src/flash/mod.rs b/libboard_zynq/src/flash/mod.rs index e53d7d7..3d2df2a 100644 --- a/libboard_zynq/src/flash/mod.rs +++ b/libboard_zynq/src/flash/mod.rs @@ -184,7 +184,6 @@ impl Flash<()> { slcr::MioPin00::zeroed() .l0_sel(true) .io_type(slcr::IoBufferType::Lvcmos18) - .pullup(true) ); // Option: Add Second Serial Clock @@ -193,6 +192,7 @@ impl Flash<()> { slcr::MioPin09::zeroed() .l0_sel(true) .io_type(slcr::IoBufferType::Lvcmos18) + .pullup(true) ); // Option: Add 4-bit Data @@ -201,21 +201,25 @@ impl Flash<()> { slcr::MioPin10::zeroed() .l0_sel(true) .io_type(slcr::IoBufferType::Lvcmos18) + .pullup(true) ); slcr.mio_pin_11.write( slcr::MioPin11::zeroed() .l0_sel(true) .io_type(slcr::IoBufferType::Lvcmos18) + .pullup(true) ); slcr.mio_pin_12.write( slcr::MioPin12::zeroed() .l0_sel(true) .io_type(slcr::IoBufferType::Lvcmos18) + .pullup(true) ); slcr.mio_pin_13.write( slcr::MioPin13::zeroed() .l0_sel(true) .io_type(slcr::IoBufferType::Lvcmos18) + .pullup(true) ); // Option: Add Feedback Output Clock @@ -224,6 +228,7 @@ impl Flash<()> { slcr::MioPin08::zeroed() .l0_sel(true) .io_type(slcr::IoBufferType::Lvcmos18) + .pullup(true) ); }); } diff --git a/libboard_zynq/src/slcr.rs b/libboard_zynq/src/slcr.rs index 705eaca..98c0a95 100644 --- a/libboard_zynq/src/slcr.rs +++ b/libboard_zynq/src/slcr.rs @@ -626,7 +626,7 @@ register_bit!(ddriob_ddr_ctrl, refio_en, 9); register!(ddriob_dci_ctrl, DdriobDciCtrl, RW, u32); register_bit!(ddriob_dci_ctrl, reset, 0); -register_bit!(ddriob_dci_ctrl, enable, 0); +register_bit!(ddriob_dci_ctrl, enable, 1); register_bits!(ddriob_dci_ctrl, nref_opt1, u8, 6, 7); register_bits!(ddriob_dci_ctrl, nref_opt2, u8, 8, 10); register_bits!(ddriob_dci_ctrl, nref_opt4, u8, 11, 13);