From 43b6d3acd038a35628f92701d3eec1d2ce92bbda Mon Sep 17 00:00:00 2001 From: Astro Date: Tue, 21 May 2019 02:53:59 +0200 Subject: [PATCH] uart: wait for reset --- src/slcr.rs | 20 ++++++++++++++++---- src/uart/mod.rs | 31 ++++++++++++++++++------------- src/uart/regs.rs | 9 +++++++++ 3 files changed, 43 insertions(+), 17 deletions(-) diff --git a/src/slcr.rs b/src/slcr.rs index 697dc6f..2dcbb05 100644 --- a/src/slcr.rs +++ b/src/slcr.rs @@ -96,12 +96,24 @@ register_bit!(uart_rst_ctrl, uart1_cpu1x_rst, 0); register_at!(UartRstCtrl, 0xF8000228, new); impl UartRstCtrl { pub fn reset_uart0(&self) { - self.modify(|_, w| w.uart0_ref_rst(true)); - self.modify(|_, w| w.uart0_ref_rst(false)); + self.modify(|_, w| + w.uart0_ref_rst(true) + .uart0_cpu1x_rst(true) + ); + self.modify(|_, w| + w.uart0_ref_rst(false) + .uart0_cpu1x_rst(false) + ); } pub fn reset_uart1(&self) { - self.modify(|_, w| w.uart1_ref_rst(true)); - self.modify(|_, w| w.uart1_ref_rst(false)); + self.modify(|_, w| + w.uart1_ref_rst(true) + .uart1_cpu1x_rst(true) + ); + self.modify(|_, w| + w.uart1_ref_rst(false) + .uart1_cpu1x_rst(false) + ); } } diff --git a/src/uart/mod.rs b/src/uart/mod.rs index 806d882..dc690f0 100644 --- a/src/uart/mod.rs +++ b/src/uart/mod.rs @@ -7,14 +7,6 @@ use crate::regs::*; mod regs; -#[repr(u8)] -pub enum ParityMode { - EvenParity = 0b000, - OddParity = 0b001, - ForceTo0 = 0b010, - ForceTo1 = 0b011, -} - pub struct Uart { regs: &'static mut regs::RegisterBlock, } @@ -63,24 +55,28 @@ impl Uart { // * 1 stop bit // * Normal channel mode // * no parity - let parity_mode = ParityMode::ForceTo0; + let parity_mode = regs::ParityMode::None; self.regs.mode.write( regs::Mode::zeroed() .par(parity_mode as u8) - .chmode(regs::ChannelMode::AutomaticEcho as u8) + .chmode(regs::ChannelMode::Normal as u8) ); // Configure the Baud Rate self.disable_rx(); self.disable_tx(); - // 115,200 baud - self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(0x28B)); - self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(0xF)); + // 9,600 baud + self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(651)); + self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(7)); + // // 115,200 baud + // self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(62)); + // self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(6)); // Enable controller self.reset_rx(); self.reset_tx(); + self.wait_reset(); self.enable_rx(); self.enable_tx(); @@ -128,6 +124,15 @@ impl Uart { }) } + /// Wait for `reset_rx()` or `reset_tx()` to complete + fn wait_reset(&self) { + let mut pending = true; + while pending { + let control = self.regs.control.read(); + pending = control.rxrst() || control.txrst(); + } + } + fn set_break(&self, startbrk: bool, stopbrk: bool) { self.regs.control.modify(|_, w| { w.sttbrk(startbrk) diff --git a/src/uart/regs.rs b/src/uart/regs.rs index 7cd0174..11ebccb 100644 --- a/src/uart/regs.rs +++ b/src/uart/regs.rs @@ -9,6 +9,15 @@ pub enum ChannelMode { RemoteLoopback = 0b11, } +pub enum ParityMode { + EvenParity = 0b000, + OddParity = 0b001, + ForceTo0 = 0b010, + ForceTo1 = 0b011, + None = 0b111, +} + + #[repr(C)] pub struct RegisterBlock { pub control: Control,