From 402b8c9ab1c3ef5281047393fbcdab8106c7f072 Mon Sep 17 00:00:00 2001 From: Astro Date: Thu, 23 May 2019 23:18:17 +0200 Subject: [PATCH] eth: no unsafe, note, add qbar register fields --- src/eth/mod.rs | 9 +++++---- src/eth/regs.rs | 2 ++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/eth/mod.rs b/src/eth/mod.rs index 049dfd5..8fb88ec 100644 --- a/src/eth/mod.rs +++ b/src/eth/mod.rs @@ -8,15 +8,15 @@ pub struct Eth { impl Eth { pub fn gem0() -> Self { - let regs = unsafe { regs::RegisterBlock::gem0() }; + let regs = regs::RegisterBlock::gem0(); Eth { regs }.init() } - + pub fn gem1() -> Self { - let regs = unsafe { regs::RegisterBlock::gem1() }; + let regs = regs::RegisterBlock::gem1(); Eth { regs }.init() } - + fn init(self) -> Self { // Clear the Network Control register. self.regs.net_ctrl.write(regs::NetCtrl::zeroed()); @@ -39,6 +39,7 @@ impl Eth { .tx_complete(true) .tx_under_run(true) .late_collision(true) + // not in the manual: .hresp_not_ok(true) ); // Disable all interrupts. diff --git a/src/eth/regs.rs b/src/eth/regs.rs index 8de487e..f0ad450 100644 --- a/src/eth/regs.rs +++ b/src/eth/regs.rs @@ -144,8 +144,10 @@ register_bit!(rx_status, rx_overrun, 2); register_bit!(rx_status, hresp_not_ok, 3); register!(rx_qbar, RxQbar, RW, u32); +register_bits!(rx_qbar, rx_q_baseaddr, u32, 2, 31); register!(tx_qbar, TxQbar, RW, u32); +register_bits!(tx_qbar, tx_q_baseaddr, u32, 2, 31); register!(intr_dis, IntrDis, WO, u32); register_bit!(intr_dis, mgmt_done, 0);