diff --git a/content/experiment-control/sinara-core.md b/content/experiment-control/sinara-core.md
index 2a849d8..a475c65 100644
--- a/content/experiment-control/sinara-core.md
+++ b/content/experiment-control/sinara-core.md
@@ -210,6 +210,26 @@ The Sinara 7210 is a low-noise clock distribution module that can be used to dis
 {% end %}
 
 
+{% layout_text_img(src="images/phaser@2x.png", popup="images/origin/phaser.jpg", alt="", shadow=false) %}
+
+##### Sinara 4624 AWG "Phaser"
+
+The 4624 AWG "Phaser" is a quad channel 1.25 GS/s RF generator card with dual IQ upconverter and dual 5 MS/s ADC and FPGA in EEM form factor.
+
+- 2x 1.25 GS/s IQ upconverters.
+- dual IQ mixer + 0.3 GHz to 4.8 GHz VCO + PLL.
+- 31.5 dB range digital step attenuator (similar to Urukul).
+- 2 channels of 5 MS/s ADC (similar to Sampler).
+- Artix-7 FPGA.
+- Internal MMCX clock from Kasli/Clocker and external SMA.
+- Upconverter is optional.
+- DDR3 SDRAM (currently not used by gateware).
+- The gateware support is currently limited to the <a href="https://github.com/quartiq/Phaser_STFT_Pulsegen" target="_blank" rel="noopener noreferrer">STFT pulse generator</a>. Other applications are possible in theory (including arbitrary waveform buffer in SDRAM), please contact us.
+
+<a href="https://github.com/sinara-hw/Phaser/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
+{% end %}
+
 
 {{ layout_separator_empty() }}
 
diff --git a/static/images/origin/phaser.jpg b/static/images/origin/phaser.jpg
new file mode 100644
index 0000000..bcb47ed
Binary files /dev/null and b/static/images/origin/phaser.jpg differ
diff --git a/static/images/phaser@2x.png b/static/images/phaser@2x.png
new file mode 100644
index 0000000..cf3be51
Binary files /dev/null and b/static/images/phaser@2x.png differ