forked from M-Labs/nac3
nac3artiq: add stubs for now-pinning on rv32g (#97)
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d6b92adf70
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nac3artiq/src
@ -212,7 +212,7 @@ impl Nac3 {
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};
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};
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let time_fns: &(dyn TimeFns + Sync) = match isa {
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let time_fns: &(dyn TimeFns + Sync) = match isa {
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Isa::Host => &timeline::EXTERN_TIME_FNS,
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Isa::Host => &timeline::EXTERN_TIME_FNS,
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Isa::RiscV32G => &timeline::NOW_PINNING_TIME_FNS,
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Isa::RiscV32G => &timeline::NOW_PINNING_TIME_FNS_64,
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Isa::RiscV32IMA => &timeline::NOW_PINNING_TIME_FNS,
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Isa::RiscV32IMA => &timeline::NOW_PINNING_TIME_FNS,
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Isa::CortexA9 => &timeline::EXTERN_TIME_FNS,
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Isa::CortexA9 => &timeline::EXTERN_TIME_FNS,
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};
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};
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@ -7,6 +7,26 @@ pub trait TimeFns {
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fn emit_delay_mu<'ctx, 'a>(&self, ctx: &mut CodeGenContext<'ctx, 'a>, dt: BasicValueEnum<'ctx>);
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fn emit_delay_mu<'ctx, 'a>(&self, ctx: &mut CodeGenContext<'ctx, 'a>, dt: BasicValueEnum<'ctx>);
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}
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}
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pub struct NowPinningTimeFns64 {}
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// For FPGA design reasons, on VexRiscv with 64-bit data bus, the "now" CSR is split into two 32-bit
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// values that are each padded to 64-bits.
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impl TimeFns for NowPinningTimeFns64 {
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fn emit_now_mu<'ctx, 'a>(&self, ctx: &mut CodeGenContext<'ctx, 'a>) -> BasicValueEnum<'ctx> {
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unimplemented!();
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}
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fn emit_at_mu<'ctx, 'a>(&self, ctx: &mut CodeGenContext<'ctx, 'a>, t: BasicValueEnum<'ctx>) {
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unimplemented!();
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}
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fn emit_delay_mu<'ctx, 'a>(&self, ctx: &mut CodeGenContext<'ctx, 'a>, dt: BasicValueEnum<'ctx>) {
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unimplemented!();
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}
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}
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pub static NOW_PINNING_TIME_FNS_64: NowPinningTimeFns64 = NowPinningTimeFns64 {};
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pub struct NowPinningTimeFns {}
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pub struct NowPinningTimeFns {}
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impl TimeFns for NowPinningTimeFns {
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impl TimeFns for NowPinningTimeFns {
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