forked from sinara-hw/datasheets
196 lines
8.1 KiB
TeX
196 lines
8.1 KiB
TeX
\input{preamble.tex}
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\graphicspath{{images}, {images/4624}}
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\title{4624 AWG Phaser}
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\author{M-Labs Limited}
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\date{January 2025}
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\revision{Revision 0}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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\maketitle
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\section{Features}
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\begin{itemize}
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\item{4 channels of 1.25 GSPS 16-bit DAC}
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\item{2 channels of 5 MSPS ADC}
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\item{dual IQ mixer + 0.3 GHz to 4.8 GHz VCO + PLL}
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\item{31.5 dB range DDS}
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\item{Xilinx Artix-7 FPGA core}
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\item{DDR3 SDRAM}
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\end{itemize}
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\section{Applications}
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\begin{itemize}
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% placeholders/guessing. STFT requires alternate gateware?
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\item{? phase control for quantum gates?}
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\item{? laser modulation?}
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\item{?? STFT pulse generator?}
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\end{itemize}
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\section{General Description}
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4624 AWG Phaser is an 8hp EEM form factor module, part of the ARTIQ/Sinara family. It adds versatile arbitrary wave generation (AWG) capabilities to carrier cards such as Kasli 2.0 and Kasli-SoC, with quadrature modulation compensation and interpolation features. It is available in two variants: Upconverter, which includes integrated RF upconversion, and Baseband, without it.
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Each card supplies four channels of digital-to-analog conversion (DAC) at 1.25 GSPS and two channels of analog-to-digital conversion (ADC) at 5 MSPS. The Upconverter variant features dual IQ (Quadrature) mixers with voltage-controlled oscillators for precise frequency generation and modulation. % Input channels can be terminated at 50 Ω, individually controllable using DIP switches. Output channels can be attenuated from 0 to -31.5 dB by a digital attenuator.
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Multiple gateware variants exist for 4624 AWG Phaser, including MIQRO, available separately from QUARTIQ, which is capable of generating up to 16 dynamic tones.
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% Switch to next column
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\vfill\break
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%\begin{figure}[h]
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% \centering
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% \scalebox{1.15}{
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% \begin{circuitikz}[european, every label/.append style={align=center}]
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% \begin{scope}[]
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% % if applicable
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% \end{scope}
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% \end{circuitikz}
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% }
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% \caption{Simplified Block Diagram}
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%\end{figure}
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\begin{figure}[hbt!]
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\centering
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\includegraphics[height=2.25in]{photo4624.jpg}
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\caption{Phaser card}
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\includegraphics[height=3in, angle=90]{fp4624.pdf}
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\caption{Phaser front panel}
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\end{figure}
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% For wide tables, a single column layout is better. It can be switched
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% page-by-page.
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\onecolumn
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\sourcesection{4624 AWG Phaser}{https://github.com/sinara-hw/Phaser/}
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\section{Specifications}
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% DAC: https://www.ti.com/lit/ds/symlink/dac34h84.pdf?ts=1743366540161&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDAC34H84
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% ADC: https://www.analog.com/media/en/technical-documentation/data-sheets/232316fc.pdf
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% si510: https://www.mouser.com/datasheet/2/368/si510-11-767375.pdf
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% IQ mixer: https://www.ti.com/lit/gpn/trf372017
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% FPGA: Artix-7 XC7A100T
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\begin{table}[hbt!]
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\centering
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\begin{threeparttable}
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\caption{Component Specifications}
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\begin{tabularx}{\textwidth}{l | c c c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
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\textbf{Unit} & \textbf{Conditions} \\
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\hline
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DAC & & & & & \\
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\hspace{3mm} Resolution & & 16 & & bits & \\
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\hspace{3mm} Sample rate & & 1.25 & & GSPS & \\
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% \hspace{3mm} DDS frequency & -500 & & 500 & MHz \\ ? from sftf paper
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\hline
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Output voltage & & ? & & & \\
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\hline
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Output digital attenuation & -31.5 & & 0 & dB & \\
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\hline
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ADC & & & & & \\
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\hspace{3mm} Resolution & & 16 & & bits & \\
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\hspace{3mm} Throughput rate & & 5 & & MSPS & \\
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\hspace{3mm} Input voltage & & ? & & & \\
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\hline
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Interpolater & & & & & \\ % is this STFT gateware specific?
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\hspace{3mm} Image rejection & 89.5 & & & dB & \\
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\hline
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\hspace{3mm} Passband droop & \multicolumn{4}{c|}{ 0.9 dB/10\%} & \\
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\hspace{3mm} Input cutoff frequency & \multicolumn{4}{c|} {80\% of Nyquist} & \\ % can this be a number
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\hspace{3mm} Interpolation rate & & ? & & & \\
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\hline
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Upconverter & & & & & \\
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\hspace{3mm} Resolution & & 58 & & mHz & \\
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\hspace{3mm} Range & -250 & & 250 & MHz & \\
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\hspace{3mm} Signal to noise ratio & 83 & & & dB & \\
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\hspace{3mm} Spur-free dynamic range & & 84 & & dB & \\
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\hline
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DC Input signal impedance & \multicolumn{4}{c|}{100 k$\Omega$} & Termination off\\
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& \multicolumn{4}{c|}{50 $\Omega$} & Termination on \\
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\hline
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PLL/VCO & & & & & \\
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\hspace{3mm} LO frequency & 0.3 & & 4.8 & GHz & \\
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\thickhline
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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Clock input may be supplied to 4624 AWG Phaser using either the internal MMCX connector or the external SMA connector in the front panel. % Are these both actually usable with current gateware/ARTIQ?
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\section{FPGA}
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4624 AWG Phaser features a XC7A100T Xilinx Artix-7 FPGA to to facilitate reconfigurable high-speed control of wave generation, sampling, and servo capabilities. Phaser was designed as a flexible hardware platform for many different signal generation schemes; multiple gateware configurations exist, and more could be written, covering different use-cases.
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M-Labs normally provides the Phaser "classic" configuration, which hosts fixed interpolators and subsequent digital upconverters for two RF output channels. A notable alternative configuration is MIQRO, available separately from QUARTIQ, which supports up to four dynamic tones per output channel.
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\section{Phaser I/O}
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\begin{multicols}{2}
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The front panel of 4624 AWG Phaser features a total of five SMA connectors, individually labeled. The dual ADC channels are respectively exposed on \texttt{ADC IN0} and \texttt{ADC IN1}, with input termination by DIP switch (see below). Depending on configuration, the four DAC outputs are either available directly (Baseband variant) or fed in pairs to the two quadrature upconverters (Upconverter variant).
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In the Upconverter variant, outputs from the upconverters are passed through the 31.5 dB range step attenuattor and exposed in the front panel at \texttt{RF0} and \texttt{RF1}.
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\columnbreak
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\begin{center}
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\centering
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\includegraphics[height=1.7in]{phaser_mmcx.jpg}
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\captionof{figure}{Position of MMCX DAC outputs}
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\end{center}
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\end{multicols}
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\vspace{-1em}
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In the Baseband variant, two of four channels, the in-phase or even outputs, are available on \texttt{RF0} and \texttt{RF1}. Respective odd outputs are exposed by labeled MMCX connectors at back of board.
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\subsection{LEDs}
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4624 AWG Phaser provides six user LEDs, which are located in the front panel. % Which? There seem to be at least 9, but the control function is six-bit.
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These are directly accessible in ARTIQ gateware and can be used for testing or feedback.
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\begin{multicols}{2}
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\section{Configuring Termination}
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The input termination must be configured by setting physical switches on the board. The termination switches are found at the middle left part of the card and are by-channel. Setting these switches to \texttt{on} adds a 50\textOmega~termination between the differential input signals.
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\vspace*{\fill}
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\columnbreak
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\begin{center}
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\centering
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\includegraphics[height=1.7in]{phaser_dip_switches.jpg}
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\captionof{figure}{Position of switches}
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\end{center}
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\end{multicols}
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\newpage
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\sysdescsection
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4624 AWG Phaser should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
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\begin{tcolorbox}[colback=white]
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\begin{minted}{json}
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{
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"type": "phaser",
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"ports": [0]
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}
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\end{minted}
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\end{tcolorbox}
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Replace 0 with the EEM port number used on the core device. Any port can be used. On Phaser's side, two EEM ports are present, but only one is necessary; this should always be \texttt{EEM0}.
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\codesection{4624 AWG Phaser}
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\ordersection{4624 AWG Phaser}
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\finalfootnote
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\end{document}
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