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.gitignore
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@ -7,4 +7,3 @@ build
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result
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result
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images/unsorted
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examples/unsorted
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92
1008.tex
92
1008.tex
@ -1,92 +0,0 @@
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\input{preamble.tex}
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\graphicspath{{images/1008}{images}}
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\title{1008 VHDCI Carrier}
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\author{M-Labs Limited}
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\date{January 2025}
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\revision{Revision 1}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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\maketitle
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\section{Features}
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\begin{itemize}
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\item{8 channels}
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\item{8 internal EEM connectors}
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\item{2 external VHDCI connectors}
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\end{itemize}
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\section{Applications}
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\begin{itemize}
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\item{Break out VHDCI to extension boards}
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\item{Carry signals over VHDCI between crates \begin{itemize}
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\item{With one for each of two crates, serves as a low-cost
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and low-latency alternative to \mbox{DRTIO} for some applications}
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\end{itemize}}
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\item{Adapter for certain KC705 ARTIQ systems}
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\end{itemize}
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\section{General Description}
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The 1008 VHDCI Carrier is a 4hp EEM module, part of the ARTIQ/Sinara family. It is a passive adapter card which converts VHDCI connects to or from EEM connections.
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The 1008 VHDCI Carrier is bidirectional; it can be driven by a core device carrier board, or can drive other cards.
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A pair of VHDCI Carrier cards can be paired with VHDCI SCSI-3 cables to carry EEM signals over short distances between crates. Depending on the application, this can serve as a simple, low-cost, low-latency alternative to multiple core devices and ARTIQ DRTIO.
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% Switch to next column
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\vfill\break
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%\begin{figure}[h]
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% \centering
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% \scalebox{1.15}{
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% \begin{circuitikz}[european, every label/.append style={align=center}]
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% \begin{scope}[]
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% % if applicable
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% \end{scope}
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% \end{circuitikz}
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% }
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% \caption{Simplified Block Diagram}
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%\end{figure}
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\begin{figure}[hbt!]
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\centering
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\includegraphics[height=2.5in]{photo1008.jpg}
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\caption{VHDCI Carrier card}
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\includegraphics[height=2.5in, angle=90]{fp1008.pdf}
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\caption{VHDCI Carrier front panel}
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\end{figure}
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% For wide tables, a single column layout is better. It can be switched
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% page-by-page.
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\onecolumn
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\sourcesection{1008 VHDCI Carrier}{https://github.com/sinara-hw/VHDCI_Carrier}
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\section{Electrical Specifications}
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\begin{table}[h]
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\centering
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\begin{threeparttable}
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\caption{Electrical Specifications}
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\begin{tabularx}{0.65\textwidth}{l | c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Max. Value} & \textbf{Unit} & \textbf{Conditions} \\
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\thickhline
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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12-V power should be supplied through the barrel jack in the front panel (2.50 mm ID, 5.50 mm OD).
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\section{Specifications}
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\ordersection{1008 VHDCI Carrier}
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\finalfootnote
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\end{document}
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3
1124.tex
3
1124.tex
@ -157,9 +157,10 @@
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\caption{Kasli 2.0 card}
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\caption{Kasli 2.0 card}
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\end{figure}
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\end{figure}
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\begin{figure}[hbt!]
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\begin{figure}[hbt!]
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\centering
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\centering
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\includegraphics[angle=90,height=0.9in]{fp1124.pdf}
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\includegraphics[angle=90,height=0.9in]{Kasli_FP.pdf}
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\caption{Kasli 2.0 front panel}
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\caption{Kasli 2.0 front panel}
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\end{figure}
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\end{figure}
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118
1550.tex
118
1550.tex
@ -1,118 +0,0 @@
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\input{preamble.tex}
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\graphicspath{{images}, {images/1550}}
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\title{1550 Laser Diode Driver Kirdy}
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\author{M-Labs Limited}
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\date{January 2025}
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\revision{Revision 1}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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\maketitle
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\section{Features}
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\begin{itemize}
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\item{300mA max output current, 20-bit resolution}
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\item{Low noise current source}
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\item{18MHz-bandwidth modulation input}
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\item{Monitor photodiode and LD protection}
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\item{Built-in sub-mK stability temperature controller}
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\item{Full digital control over Ethernet}
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\end{itemize}
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\section{Applications}
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\begin{itemize}
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\item{High-precision laser driver}
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\item{Suitable for use with adapter and preinstalled laser assembly or with external laser heads}
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\item{Spectroscopy and oher atomic physics applications}
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\end{itemize}
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\section{General Description}
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The 1550 Laser Diode Driver Kirdy is a 8hp EEM form factor module, part of the Sinara open hardware family. It serves as a precision laser diode driver, featuring a low-noise current source, low- and high-frequency modulation inputs, and full digital control over Ethernet. Soft turn-on, laser power monitoring with a user-defined trip point, overtemperature protection, and a protection relay minimize the risk of damage to the laser diode.
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1550 Kirdy supports both low-frequency modulation, suitable for laser locks and linewidth reduction, as well as RF modulation injected directly into the diode, typically to inject sidebands into the beam and implement stabilization schemes such as Pound-Drever-Hall and modulation transfer spectroscopy.
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% Switch to next column
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\vfill\break
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%\begin{figure}[h]
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% \centering
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% \scalebox{1.15}{
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% \begin{circuitikz}[european, every label/.append style={align=center}]
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% \begin{scope}[]
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% % if applicable
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% \end{scope}
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% \end{circuitikz}
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% }
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%
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% \caption{Simplified Block Diagram}
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||||||
%\end{figure}
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||||||
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||||||
\begin{figure}[hbt!]
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||||||
\centering
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\includegraphics[height=2.5in]{photo1550.jpg}
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\caption{Kirdy card photo}
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\includegraphics[height=3in, angle=90]{fp1550.pdf}
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\caption{Kirdy front panel}
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\end{figure}
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% For wide tables, a single column layout is better. It can be switched
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% page-by-page.
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\onecolumn
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\sourcesection{1550 Laser Diode Driver Kirdy}{https://git.m-labs.hk/sinara-hw/kirdy} The associated adapter can be found at the repository /url{https://git.m-labs.hk/sinara-hw/kirdyAdapter/src/branch/master}.
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\section{Adapter and Laser Options}
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An optional adapter allows compact lasers in butterfly packages to be mounted directly onto 1550 Kirdy, with a fibre-optic output in the front panel. Multiple single-frequency narrow-linewidth lasers are currently available as preinstalled options for order.
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Alternatively, Kirdy accepts laser signals broken out to the front panel and is suitable for use in driving external laser heads, including commercial or custom ECDLs (with additional piezo driver) or injection-locked Fabry-Perot diodes.
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\section{Specifications}
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||||||
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|
||||||
microcontroller datasheet: \url{https://www.st.com/resource/en/datasheet/DM00037051.pdf}
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1550 Kirdy supports Power-over-Ethernet. Alternatively, power can be provided via 12V DC input in front panel.
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300mA max output
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4V compliance
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20 bit DAC control, 50Hz bandwidth
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300pA/rt Hz current noise @ 1kHz
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|
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300nA RMS Noise (10Hz - 1MHz)
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|
||||||
Laser power monitor
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|
||||||
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|
||||||
0 - 2.5mA Photodiode current monitoring
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|
||||||
TEC Controller
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1A max output
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|
||||||
5V compliance
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|
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+- 1mK stability
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\section{Selecting modulation gain}
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|
||||||
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|
||||||
DC to 10MHz modulation input (+/- 1V max) with selectable modulation gains
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|
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0.25mA/V
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|
||||||
2.5mA/V
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|
||||||
25mA/V
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|
||||||
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|
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\section{Firmware and Linien}
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|
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|
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1550 Kirdy features front panel Ethernet and USB-C. Either DFU or OpenOCD can be used to flash firmware; OpenOCD however requires a JTAG adapter.
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|
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It can be connected in particular to the Sinara Fast-Servo and used with the Linien application that enables easy locking of lasers to spectral lines.
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|
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|
||||||
https://github.com/linien-org/linien
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|
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https://git.m-labs.hk/M-Labs/nix-servo
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\ordersection{1550 Laser Diode Driver Kirdy}.
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\finalfootnote
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\end{document}
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308
2118-2128.tex
308
2118-2128.tex
@ -4,7 +4,7 @@
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\title{2118 BNC-TTL / 2128 SMA-TTL}
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\title{2118 BNC-TTL / 2128 SMA-TTL}
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\author{M-Labs Limited}
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\author{M-Labs Limited}
|
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\date{January 2022}
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\date{January 2022}
|
||||||
\revision{Revision 2}
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\revision{Revision 3}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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\begin{document}
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@ -13,30 +13,30 @@
|
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\section{Features}
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\section{Features}
|
||||||
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|
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\begin{itemize}
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\begin{itemize}
|
||||||
\item{8 TTL channels}
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\item{8 TTL channels}
|
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\item{Input- and output-capable}
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\item{Input- and output-capable}
|
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\item{Galvanically isolated}
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\item{Galvanically isolated}
|
||||||
\item{3ns minimum pulse width}
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\item{3ns minimum pulse width}
|
||||||
\item{BNC or SMA connectors}
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\item{BNC or SMA connectors}
|
||||||
\end{itemize}
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\end{itemize}
|
||||||
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|
||||||
\section{Applications}
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\section{Applications}
|
||||||
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|
||||||
\begin{itemize}
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\begin{itemize}
|
||||||
\item{Photon counting}
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\item{Photon counting}
|
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\item{External equipment trigger}
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\item{External equipment trigger}
|
||||||
\item{Optical shutter control}
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\item{Optical shutter control}
|
||||||
\end{itemize}
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\end{itemize}
|
||||||
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|
||||||
\section{General Description}
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\section{General Description}
|
||||||
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|
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The 2118 BNC-TTL card is an 8hp EEM module; the 2128 SMA-TTL is a 4hp EEM module. Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
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The 2118 BNC-TTL card is an 8hp EEM module; the 2128 SMA-TTL is a 4hp EEM module. Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||||
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|
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Each card provides two banks of four digital channels, for a total of eight digital channels, with respectively either BNC (2118) or SMA (2128) connectors. Each bank possesses individual ground isolation. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
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Each card provides two banks of four digital channels, for a total of eight digital channels, with respectively either BNC (2118) or SMA (2128) connectors. Each bank possesses individual ground isolation. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
|
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|
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Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely. Both cards are capable of a minimum pulse width of 3ns.
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Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely. Both cards are capable of a minimum pulse width of 3ns.
|
||||||
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|
||||||
Note that isolated TTL cards are less suited to low-noise applications as the isolator itself injects noise between primary and secondary sides. Cable shields may also radiate EMI from the isolated grounds. For low-noise applications, use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
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Isolated TTL cards are not well suited to low-noise or low-jitter applications due to interference from isolation components. For low-noise applications, use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
|
||||||
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% Switch to next column
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% Switch to next column
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\vfill\break
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\vfill\break
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@ -295,11 +295,11 @@ Note that isolated TTL cards are less suited to low-noise applications as the is
|
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\begin{figure}[hbt!]
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\begin{figure}[hbt!]
|
||||||
\centering
|
\centering
|
||||||
\includegraphics[height=1.8in]{photo2118-2128.jpg }
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\includegraphics[height=1.8in]{photo2118-2128.jpg }
|
||||||
\caption{BNC-TTL and SMA-TTL cards}%
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\caption{BNC-TTL and SMA-TTL cards}
|
||||||
\includegraphics[angle=90, height=0.7in]{DIO_BNC_FP.jpg}
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\includegraphics[angle=90, height=0.7in]{fp2118.jpg}
|
||||||
\includegraphics[angle=90, height=0.4in]{DIO_SMA_FP.jpg}
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\includegraphics[angle=90, height=0.4in]{fp2128.jpg}
|
||||||
\caption{BNC-TTL and SMA-TTL front panels}%
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\caption{BNC-TTL and SMA-TTL front panels}
|
||||||
\label{fig:example}%
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\label{fig:example}
|
||||||
\end{figure}
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\end{figure}
|
||||||
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|
||||||
\onecolumn
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\onecolumn
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||||||
@ -307,159 +307,185 @@ Note that isolated TTL cards are less suited to low-noise applications as the is
|
|||||||
\sourcesectiond{2118 BNC-TTL}{2128 SMA-TTL}{https://github.com/sinara-hw/DIO_BNC}{https://github.com/sinara-hw/DIO_SMA}
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\sourcesectiond{2118 BNC-TTL}{2128 SMA-TTL}{https://github.com/sinara-hw/DIO_BNC}{https://github.com/sinara-hw/DIO_SMA}
|
||||||
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|
||||||
\section{Electrical Specifications}
|
\section{Electrical Specifications}
|
||||||
All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
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All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
|
||||||
Specifications were derived based on the datasheets of the bus transceiver IC (SN74BCT25245DW\footnote{\label{transceiver}\url{https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf}}) and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}}). The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}\url{https://github.com/sinara-hw/sinara/issues/187}}.
|
Specifications were derived based on the datasheets of the bus transceiver IC (SN74BCT25245DW\footnote{\label{transceiver}\url{https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf}}) and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}}). The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}\url{https://github.com/sinara-hw/sinara/issues/187}}.
|
||||||
|
|
||||||
\begin{table}[h]
|
\begin{table}[h]
|
||||||
\begin{threeparttable}
|
\begin{threeparttable}
|
||||||
\caption{Recommended Operating Conditions}
|
\caption{Recommended Operating Conditions}
|
||||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||||
\thickhline
|
\thickhline
|
||||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||||
\textbf{Unit} & \textbf{Conditions} \\
|
\textbf{Unit} & \textbf{Conditions} \\
|
||||||
\hline
|
\hline
|
||||||
High-level input voltage\repeatfootnote{transceiver} & 2 & & 5.5* & V & \\
|
High-level input voltage\repeatfootnote{transceiver} & 2 & & 5.5* & V & \\
|
||||||
\hline
|
\hline
|
||||||
Low-level input voltage\repeatfootnote{transceiver} & -0.5 & & 0.8 & V & \\
|
Low-level input voltage\repeatfootnote{transceiver} & -0.5 & & 0.8 & V & \\
|
||||||
\hline
|
\hline
|
||||||
Input clamp current\repeatfootnote{transceiver} & & & -18 & mA & termination disabled \\
|
Input clamp current\repeatfootnote{transceiver} & & & -18 & mA & termination disabled \\
|
||||||
\hline
|
\hline
|
||||||
High-level output current\repeatfootnote{transceiver} & & & -160 & mA & \\
|
High-level output current\repeatfootnote{transceiver} & & & -160 & mA & \\
|
||||||
\hline
|
\hline
|
||||||
Low-level output current\repeatfootnote{transceiver} & & & 376 & mA & \\
|
Low-level output current\repeatfootnote{transceiver} & & & 376 & mA & \\
|
||||||
\thickhline
|
\thickhline
|
||||||
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||||
\end{tabularx}
|
\end{tabularx}
|
||||||
\end{threeparttable}
|
\end{threeparttable}
|
||||||
\end{table}
|
\end{table}
|
||||||
|
|
||||||
\begin{table}[h]
|
\begin{table}[h]
|
||||||
\begin{threeparttable}
|
\begin{threeparttable}
|
||||||
\caption{Electrical Characteristics}
|
\caption{Electrical Characteristics}
|
||||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||||
\thickhline
|
\thickhline
|
||||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||||
\textbf{Unit} & \textbf{Conditions} \\
|
\textbf{Unit} & \textbf{Conditions} \\
|
||||||
\hline
|
\hline
|
||||||
High-level output voltage\repeatfootnote{transceiver} & 2 & & & V & $I_{OH}$=-160mA \\
|
High-level output voltage\repeatfootnote{transceiver} & 2 & & & V & $I_{OH}$=-160mA \\
|
||||||
& 2.7 & & & V & $I_{OH}$=-6mA \\
|
& 2.7 & & & V & $I_{OH}$=-6mA \\
|
||||||
\hline
|
\hline
|
||||||
Low-level output voltage\repeatfootnote{transceiver} & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
|
Low-level output voltage\repeatfootnote{transceiver} & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
|
||||||
& & & 0.7 & V & $I_{OL}$=376mA \\
|
& & & 0.7 & V & $I_{OL}$=376mA \\
|
||||||
\hline
|
\hline
|
||||||
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & 3 & 5 & ns & \\
|
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & 3 & 5 & ns & \\
|
||||||
\hline
|
\hline
|
||||||
Pulse width distortion\repeatfootnote{isolator} & & 0.2 & 4.5 & ns & \\
|
Pulse width distortion\repeatfootnote{isolator} & & 0.2 & 4.5 & ns & \\
|
||||||
\hline
|
\hline
|
||||||
Peak jitter\repeatfootnote{isolator} & & 350 & & ps & \\
|
Peak jitter\repeatfootnote{isolator} & & 350 & & ps & \\
|
||||||
\hline
|
\hline
|
||||||
Data rate\repeatfootnote{isolator} & 0 & & 150 & Mbps & \\
|
Data rate\repeatfootnote{isolator} & 0 & & 150 & Mbps & \\
|
||||||
\thickhline
|
\thickhline
|
||||||
\end{tabularx}
|
\end{tabularx}
|
||||||
\end{threeparttable}
|
\end{threeparttable}
|
||||||
\end{table}
|
\end{table}
|
||||||
|
|
||||||
Minimum pulse width was measured by generating pulses of progressively longer duration through a DDS generator and using them as input for a BNC-TTL card. The input BNC-TTL card was connected to another BNC-TTL card as output. The output signal is measured and shown in Figure \ref{fig:pulsewidth}.
|
Low-jitter applications should note carefully the jitter introduced by the signal isolator. Noise is also introduced between the primary and secondary domains by the DC/DC converter. Where noise or jitter are crucial, it is instead recommended to use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
|
||||||
|
|
||||||
\begin{figure}[ht]
|
Minimum pulse width was measured by generating pulses of progressively longer duration through a DDS generator and using them as input for a BNC-TTL card. The input BNC-TTL card was connected to another BNC-TTL card as output. The output signal is measured and shown in Figure \ref{fig:pulsewidth}.
|
||||||
\centering
|
|
||||||
\includegraphics[height=3in]{bnc_ttl_min_pulse_width.png}
|
\begin{figure}[ht]
|
||||||
\caption{Minimum pulse width required for BNC-TTL card}
|
\centering
|
||||||
\label{fig:pulsewidth}
|
\includegraphics[height=3in]{bnc_ttl_min_pulse_width.png}
|
||||||
\end{figure}
|
\caption{Minimum pulse width required for BNC-TTL card}
|
||||||
|
\label{fig:pulsewidth}
|
||||||
|
\end{figure}
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
|
|
||||||
The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly.
|
The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly.
|
||||||
|
|
||||||
\section{Configuring IO Direction \& Termination}
|
\section{Configuring IO Direction \& Termination}
|
||||||
|
|
||||||
IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank.
|
IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank.
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\itemsep0em
|
\itemsep0em
|
||||||
\item IO direction switch closed (\texttt{ON}) \\
|
\item IO direction switch closed (\texttt{ON}) \\
|
||||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||||
\item IO direction switch open (OFF) \\
|
\item IO direction switch open (OFF) \\
|
||||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\begin{figure}[hbt!]
|
\begin{figure}[hbt!]
|
||||||
\centering
|
\centering
|
||||||
\subfloat[\centering BNC-TTL]{{
|
\subfloat[\centering BNC-TTL]{{
|
||||||
\includegraphics[height=1.5in]{bnc_ttl_switches.jpg}
|
\includegraphics[height=1.5in]{bnc_ttl_switches.jpg}
|
||||||
}}%
|
}}%
|
||||||
\subfloat[\centering SMA-TTL]{{
|
\subfloat[\centering SMA-TTL]{{
|
||||||
\includegraphics[height=1.5in]{sma_ttl_switches.jpg}
|
\includegraphics[height=1.5in]{sma_ttl_switches.jpg}
|
||||||
}}%
|
}}%
|
||||||
\caption{Position of switches}%
|
\caption{Position of switches}%
|
||||||
\end{figure}
|
\end{figure}
|
||||||
|
|
||||||
|
\sysdescsection
|
||||||
|
|
||||||
|
2118 BNC-TTL and 2128 SMA-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||||
|
|
||||||
|
\begin{tcolorbox}[colback=white]
|
||||||
|
\begin{minted}{json}
|
||||||
|
"name" : {
|
||||||
|
"type": "dio",
|
||||||
|
"board": "DIO_BNC", // or "DIO_SMA", optional
|
||||||
|
"ports": [0],
|
||||||
|
"edge_counter": true, // optional
|
||||||
|
"bank_direction_low": "input", // or "output"
|
||||||
|
"bank_direction_high": "output" // or "input"
|
||||||
|
}
|
||||||
|
\end{minted}
|
||||||
|
\end{tcolorbox}
|
||||||
|
|
||||||
|
Replace 0 with the EEM port number used on the core device. Any port can be used. The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false.
|
||||||
|
|
||||||
\newpage
|
|
||||||
\codesection{2118 BNC-TTL/2128 SMA-TTL cards}
|
\codesection{2118 BNC-TTL/2128 SMA-TTL cards}
|
||||||
|
|
||||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||||
|
|
||||||
\subsection{One pulse per second}
|
\subsection{One pulse per second}
|
||||||
The channel should be configured as output in both the gateware and hardware.
|
The channel should be configured as output in both the gateware and hardware.
|
||||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||||
|
|
||||||
\subsection{Morse code}
|
|
||||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
|
||||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
\subsection{Sub-coarse-RTIO-cycle pulse}
|
|
||||||
With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
|
|
||||||
|
|
||||||
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
|
\subsection{Morse code}
|
||||||
|
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||||
|
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||||
|
|
||||||
\subsection{Edge counting in a 1ms window}
|
\subsection{Sub-coarse-RTIO-cycle pulse}
|
||||||
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
|
With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
|
||||||
The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
|
|
||||||
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
|
|
||||||
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
|
|
||||||
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
|
|
||||||
The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
|
|
||||||
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
|
|
||||||
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
|
|
||||||
|
|
||||||
The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
|
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
\subsection{Edge counting using \texttt{EdgeCounter}}
|
|
||||||
This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
|
||||||
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
|
|
||||||
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle. Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
|
|
||||||
|
|
||||||
\subsection{Responding to an external trigger}
|
\subsection{Edge counting in a 1ms window}
|
||||||
One channel needs to be configured as input, and the other as output.
|
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
|
||||||
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
|
The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
|
||||||
|
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
|
||||||
|
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
|
||||||
|
|
||||||
\subsection{62.5 MHz clock signal generation}
|
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
|
||||||
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal. Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle. Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2.
|
The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
|
||||||
|
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
|
||||||
|
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
|
||||||
|
|
||||||
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
|
The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
|
||||||
|
|
||||||
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
|
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
\subsection{Minimum sustained event separation}
|
|
||||||
The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
|
|
||||||
|
|
||||||
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
|
\subsection{Edge counting using \texttt{EdgeCounter}}
|
||||||
|
This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||||
|
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
|
||||||
|
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle. Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
|
||||||
|
|
||||||
\begin{center}
|
\subsection{Responding to an external trigger}
|
||||||
\begin{table}[H]
|
One channel needs to be configured as input, and the other as output.
|
||||||
\captionof{table}{Minimum sustained event separation of different carriers}
|
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
|
||||||
\centering
|
|
||||||
\begin{tabular}{|c|c|c|}
|
\subsection{62.5 MHz clock signal generation}
|
||||||
\hline
|
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal. Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle. Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2.
|
||||||
Carrier & Kasli v1.1 & Kasli-SoC \\ \hline
|
|
||||||
Duration & 650 ns & 600 ns \\ \hline
|
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
|
||||||
\end{tabular}
|
|
||||||
\end{table}
|
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
|
||||||
\end{center}
|
|
||||||
|
\newpage
|
||||||
|
|
||||||
|
\subsection{Minimum sustained event separation}
|
||||||
|
The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
|
||||||
|
|
||||||
|
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
|
||||||
|
|
||||||
|
\begin{center}
|
||||||
|
\begin{table}[H]
|
||||||
|
\captionof{table}{Minimum sustained event separation of different carriers}
|
||||||
|
\centering
|
||||||
|
\begin{tabular}{|c|c|c|}
|
||||||
|
\hline
|
||||||
|
Carrier & Kasli v1.1 & Kasli-SoC \\ \hline
|
||||||
|
Duration & 650 ns & 600 ns \\ \hline
|
||||||
|
\end{tabular}
|
||||||
|
\end{table}
|
||||||
|
\end{center}
|
||||||
|
|
||||||
\ordersection{2118 BNC-TTL/2128 SMA-TTL}
|
\ordersection{2118 BNC-TTL/2128 SMA-TTL}
|
||||||
|
|
||||||
|
|||||||
226
2238.tex
226
2238.tex
@ -4,7 +4,7 @@
|
|||||||
\title{2238 MCX-TTL}
|
\title{2238 MCX-TTL}
|
||||||
\author{M-Labs Limited}
|
\author{M-Labs Limited}
|
||||||
\date{January 2022}
|
\date{January 2022}
|
||||||
\revision{Revision 2}
|
\revision{Revision 3}
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||||
|
|
||||||
\begin{document}
|
\begin{document}
|
||||||
@ -13,28 +13,28 @@
|
|||||||
\section{Features}
|
\section{Features}
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\item{16 MCX-TTL channels}
|
\item{16 MCX-TTL channels}
|
||||||
\item{Input and output capable}
|
\item{Input and output capable}
|
||||||
\item{No galvanic isolation}
|
\item{No galvanic isolation}
|
||||||
\item{High speed and low jitter}
|
\item{High speed and low jitter}
|
||||||
\item{MCX connectors}
|
\item{MCX connectors}
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\section{Applications}
|
\section{Applications}
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\item{Photon counting}
|
\item{Photon counting}
|
||||||
\item{External equipment trigger}
|
\item{External equipment trigger}
|
||||||
\item{Optical shutter control}
|
\item{Optical shutter control}
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\section{General Description}
|
\section{General Description}
|
||||||
|
|
||||||
The 2238 MCX-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
The 2238 MCX-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||||
|
|
||||||
Each card provides four banks of four digital channels each for a total of sixteen digital channels, with MCX connectors in the front panel, controlled through two EEM connectors. Each individual EEM connector controls two banks independently. Single EEM operation is possible. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
|
Each card provides four banks of four digital channels each for a total of sixteen digital channels, with MCX connectors in the front panel, controlled through two EEM connectors. Each individual EEM connector controls two banks independently. Single EEM operation is possible. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
|
||||||
|
|
||||||
Each channel supports 50\textOmega~terminations individually controllable using DIP switches. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
|
Each channel supports 50\textOmega~terminations individually controllable using DIP switches. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
|
||||||
|
|
||||||
% Switch to next column
|
% Switch to next column
|
||||||
\vfill\break
|
\vfill\break
|
||||||
@ -439,7 +439,7 @@ Each channel supports 50\textOmega~terminations individually controllable using
|
|||||||
\centering
|
\centering
|
||||||
\includegraphics[height=2in]{photo2238.jpg}
|
\includegraphics[height=2in]{photo2238.jpg}
|
||||||
\caption{MCX-TTL card}
|
\caption{MCX-TTL card}
|
||||||
\includegraphics[angle=90, height=0.6in]{DIO_MCX_FP.pdf}
|
\includegraphics[angle=90, height=0.6in]{fp2238.pdf}
|
||||||
\caption{MCX-TTL front panel}
|
\caption{MCX-TTL front panel}
|
||||||
\end{figure}
|
\end{figure}
|
||||||
|
|
||||||
@ -451,104 +451,142 @@ Each channel supports 50\textOmega~terminations individually controllable using
|
|||||||
|
|
||||||
\section{Electrical Specifications}
|
\section{Electrical Specifications}
|
||||||
|
|
||||||
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the bus transceiver IC (74LVT162245MTD\footnote{\label{transceiver}\url{https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}}).
|
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the bus transceiver IC (74LVT162245MTD\footnote{\label{transceiver}\url{https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}}).
|
||||||
|
|
||||||
\begin{table}[h]
|
\begin{table}[h]
|
||||||
\begin{threeparttable}
|
\begin{threeparttable}
|
||||||
\caption{Recommended Operating Conditions}
|
\caption{Recommended Operating Conditions}
|
||||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||||
\thickhline
|
\thickhline
|
||||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||||
\textbf{Unit} & \textbf{Conditions} \\
|
\textbf{Unit} & \textbf{Conditions} \\
|
||||||
\hline
|
\hline
|
||||||
Input voltage & 0 & & 5.5* & V \\
|
Input voltage & 0 & & 5.5* & V \\
|
||||||
\hline
|
\hline
|
||||||
High-level output current & & & -24 & mA \\
|
High-level output current & & & -24 & mA \\
|
||||||
\hline
|
\hline
|
||||||
Low-level output current & & & 24 & mA \\
|
Low-level output current & & & 24 & mA \\
|
||||||
\hline
|
\hline
|
||||||
Input edge rate & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
|
Input edge rate & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
|
||||||
\thickhline
|
\thickhline
|
||||||
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||||
\end{tabularx}
|
\end{tabularx}
|
||||||
\end{threeparttable}
|
\end{threeparttable}
|
||||||
\end{table}
|
\end{table}
|
||||||
|
|
||||||
\begin{table}[h]
|
\begin{table}[h]
|
||||||
\begin{threeparttable}
|
\begin{threeparttable}
|
||||||
\caption{Electrical Characteristics}
|
\caption{Electrical Characteristics}
|
||||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||||
\thickhline
|
\thickhline
|
||||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||||
\textbf{Unit} & \textbf{Conditions} \\
|
\textbf{Unit} & \textbf{Conditions} \\
|
||||||
\hline
|
\hline
|
||||||
Input clamp diode voltage & & & -1.2 & V & $I_I =-36 mA$ \\
|
Input clamp diode voltage & & & -1.2 & V & $I_I =-36 mA$ \\
|
||||||
\hline
|
\hline
|
||||||
Input high voltage & 2.0 & & & V & \\
|
Input high voltage & 2.0 & & & V & \\
|
||||||
\hline
|
\hline
|
||||||
Input low voltage & & & 0.8 & V & \\
|
Input low voltage & & & 0.8 & V & \\
|
||||||
\hline
|
\hline
|
||||||
Output high voltage & 2.0 & & & V & $I_{OH}=-24mA$ \\
|
Output high voltage & 2.0 & & & V & $I_{OH}=-24mA$ \\
|
||||||
& 3.1 & & & V & $I_{OH}=-200\mu A$ \\
|
& 3.1 & & & V & $I_{OH}=-200\mu A$ \\
|
||||||
\hline
|
\hline
|
||||||
Output low voltage & & & 0.8 & V & $I_{OL}=-24mA$ \\
|
Output low voltage & & & 0.8 & V & $I_{OL}=-24mA$ \\
|
||||||
& & & 0.2 & V & $I_{OL}=-200\mu A$ \\
|
& & & 0.2 & V & $I_{OL}=-200\mu A$ \\
|
||||||
\hline
|
\hline
|
||||||
Input current & & & 20 & \textmu A & $V_I=5.5V$ \\
|
Input current & & & 20 & \textmu A & $V_I=5.5V$ \\
|
||||||
& & & 2 & \textmu A & $V_I=3.3V$ \\
|
& & & 2 & \textmu A & $V_I=3.3V$ \\
|
||||||
& & & -10 & \textmu A & $V_I=0V$ \\
|
& & & -10 & \textmu A & $V_I=0V$ \\
|
||||||
\thickhline
|
\thickhline
|
||||||
\end{tabularx}
|
\end{tabularx}
|
||||||
\end{threeparttable}
|
\end{threeparttable}
|
||||||
\end{table}
|
\end{table}
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
|
|
||||||
\section{Configuring IO Direction \& Termination}
|
\section{Configuring IO Direction \& Termination}
|
||||||
IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
|
|
||||||
\begin{multicols}{2}
|
|
||||||
Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
|
|
||||||
|
|
||||||
\begin{itemize}
|
IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
|
||||||
\itemsep0em
|
|
||||||
\item IO direction switch closed (\texttt{ON}) \\
|
\begin{multicols}{2}
|
||||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
|
||||||
\item IO direction switch open (OFF) \\
|
Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
|
||||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
|
||||||
\end{itemize}
|
\begin{itemize}
|
||||||
\columnbreak
|
\itemsep0em
|
||||||
\begin{center}
|
\item IO direction switch closed (\texttt{ON}) \\
|
||||||
\centering
|
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||||
\includegraphics[height=1.7in]{mcx_ttl_switches.jpg}
|
\item IO direction switch open (OFF) \\
|
||||||
\captionof{figure}{Position of switches}
|
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||||
\end{center}
|
\end{itemize}
|
||||||
\end{multicols}
|
|
||||||
|
\columnbreak
|
||||||
|
|
||||||
|
\begin{center}
|
||||||
|
\centering
|
||||||
|
\includegraphics[height=1.7in]{mcx_ttl_switches.jpg}
|
||||||
|
\captionof{figure}{Position of switches}
|
||||||
|
\end{center}
|
||||||
|
|
||||||
|
\end{multicols}
|
||||||
|
|
||||||
|
\sysdescsection
|
||||||
|
|
||||||
|
2238 MCX-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||||
|
|
||||||
|
\begin{tcolorbox}[colback=white]
|
||||||
|
\begin{minted}{json}
|
||||||
|
{
|
||||||
|
"type": "dio",
|
||||||
|
"board": "DIO_MCX", // optional
|
||||||
|
"ports": [0],
|
||||||
|
"edge_counter": true, // optional
|
||||||
|
"bank_direction_low": "input", // or "output"
|
||||||
|
"bank_direction_high": "output" // or "input"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"type": "dio",
|
||||||
|
"board": "DIO_MCX",
|
||||||
|
"ports": [1],
|
||||||
|
"bank_direction_low": "output",
|
||||||
|
"bank_direction_high": "output"
|
||||||
|
}
|
||||||
|
\end{minted}
|
||||||
|
\end{tcolorbox}
|
||||||
|
|
||||||
|
Note that due to its high channel account and double EEM connections 2238 MCX-TTL is entered into a system description as two peripheral entries, each representing two banks.
|
||||||
|
|
||||||
|
The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. Both \texttt{edge\_counter} and IO direction can be specified separately for each entry.
|
||||||
|
|
||||||
|
For single-EEM operation, use only one of two peripheral entries.
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
|
|
||||||
\codesection{2238 MCX-TTL card}
|
\codesection{2238 MCX-TTL card}
|
||||||
|
|
||||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||||
|
|
||||||
\subsection{One pulse per second}
|
\subsection{One pulse per second}
|
||||||
The channel should be configured as output in both the gateware and hardware.
|
The channel should be configured as output in both the gateware and hardware.
|
||||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||||
|
|
||||||
\subsection{Morse code}
|
\subsection{Morse code}
|
||||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
\subsection{Edge counting in an 1ms window}
|
|
||||||
The channel should be configured as input in both gateware and hardware.
|
|
||||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
|
||||||
|
|
||||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
\subsection{Edge counting in an 1ms window}
|
||||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
The channel should be configured as input in both gateware and hardware.
|
||||||
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||||
|
|
||||||
\subsection{Responding to an external trigger}
|
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||||
One channel needs to be configured as input, and the other as output.
|
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
||||||
|
|
||||||
|
\subsection{Responding to an external trigger}
|
||||||
|
One channel needs to be configured as input, and the other as output.
|
||||||
|
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||||
|
|
||||||
\ordersection{2238 MCX-TTL}
|
\ordersection{2238 MCX-TTL}
|
||||||
|
|
||||||
|
|||||||
610
2245.tex
610
2245.tex
@ -7,7 +7,7 @@
|
|||||||
\title{2245 LVDS-TTL}
|
\title{2245 LVDS-TTL}
|
||||||
\author{M-Labs Limited}
|
\author{M-Labs Limited}
|
||||||
\date{January 2022}
|
\date{January 2022}
|
||||||
\revision{Revision 2}
|
\revision{Revision 3}
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||||
|
|
||||||
\begin{document}
|
\begin{document}
|
||||||
@ -16,28 +16,28 @@
|
|||||||
\section{Features}
|
\section{Features}
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\item{16 LVDS-TTL channels.}
|
\item{16 LVDS-TTL channels.}
|
||||||
\item{Input- and output-capable}
|
\item{Input- and output-capable}
|
||||||
\item{No galvanic isolation}
|
\item{No galvanic isolation}
|
||||||
\item{High speed and low jitter}
|
\item{High speed and low jitter}
|
||||||
\item{RJ45 connectors}
|
\item{RJ45 connectors}
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\section{Applications}
|
\section{Applications}
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\item{Photon counting}
|
\item{Photon counting}
|
||||||
\item{External equipment trigger}
|
\item{External equipment trigger}
|
||||||
\item{Optical shutter control}
|
\item{Optical shutter control}
|
||||||
\item{Serial communication with remote devices}
|
\item{Serial communication with remote devices}
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\section{General Description}
|
\section{General Description}
|
||||||
The 2245 LVDS-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
The 2245 LVDS-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||||
|
|
||||||
Each card provides sixteen total digital channels, with four RJ45 connectors in the front panel, controlled through 2 EEM connectors. Each RJ45 connector exposes four LVDS digital channels. Each individual EEM connector controls eight channels independently. Single EEM operation is possible. The direction (input or output) of each channel can be selected individually using DIP switches.
|
Each card provides sixteen total digital channels, with four RJ45 connectors in the front panel, controlled through 2 EEM connectors. Each RJ45 connector exposes four LVDS digital channels. Each individual EEM connector controls eight channels independently. Single EEM operation is possible. The direction (input or output) of each channel can be selected individually using DIP switches.
|
||||||
|
|
||||||
Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~terminated. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards. Only shielded Ethernet Cat-6 cables should be connected.
|
Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~terminated. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards. Only shielded Ethernet Cat-6 cables should be connected.
|
||||||
|
|
||||||
% Switch to next column
|
% Switch to next column
|
||||||
\vfill\break
|
\vfill\break
|
||||||
@ -297,7 +297,7 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
|
|||||||
\begin{figure}[hbt!]
|
\begin{figure}[hbt!]
|
||||||
\centering
|
\centering
|
||||||
\includegraphics[angle=90, height=1.7in]{photo2245.jpg}
|
\includegraphics[angle=90, height=1.7in]{photo2245.jpg}
|
||||||
\includegraphics[angle=90, height=0.4in]{DIO_RJ45_FP.pdf}
|
\includegraphics[angle=90, height=0.4in]{fp2245.pdf}
|
||||||
\caption{LVDS-TTL card and front panel}
|
\caption{LVDS-TTL card and front panel}
|
||||||
\end{figure}
|
\end{figure}
|
||||||
|
|
||||||
@ -310,316 +310,366 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
|
|||||||
|
|
||||||
\section{Electrical Specifications}
|
\section{Electrical Specifications}
|
||||||
|
|
||||||
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
|
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
|
||||||
|
|
||||||
\begin{table}[h]
|
\begin{table}[h!]
|
||||||
\begin{threeparttable}
|
\begin{threeparttable}
|
||||||
\caption{Recommended Input Voltage}
|
\caption{Recommended Input Voltage}
|
||||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||||
\thickhline
|
\thickhline
|
||||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||||
\textbf{Unit} & \textbf{Conditions} \\
|
\textbf{Unit} & \textbf{Conditions} \\
|
||||||
\hline
|
\hline
|
||||||
Magnitude of differential input & $|V_{ID}|$ & 0.1 & & 3.3 & V \\
|
Magnitude of differential input & $|V_{ID}|$ & 0.1 & & 3.3 & V \\
|
||||||
\hline
|
\hline
|
||||||
Common mode input & $V_{IC}$ & $|V_{ID}|/2$ & & $3.3-|V_{ID}|/2$ & V \\
|
Common mode input & $V_{IC}$ & $|V_{ID}|/2$ & & $3.3-|V_{ID}|/2$ & V \\
|
||||||
\hline
|
\hline
|
||||||
Differential input threshold HIGH & $V_{TH}$ & & & 100 & mV & \\
|
Differential input threshold HIGH & $V_{TH}$ & & & 100 & mV & \\
|
||||||
\hline
|
\hline
|
||||||
Differential input threshold LOW & $V_{TL}$ & -100 & & & mV & \\
|
Differential input threshold LOW & $V_{TL}$ & -100 & & & mV & \\
|
||||||
\thickhline
|
\thickhline
|
||||||
\end{tabularx}
|
\end{tabularx}
|
||||||
\end{threeparttable}
|
\end{threeparttable}
|
||||||
\end{table}
|
\end{table}
|
||||||
|
|
||||||
All typical values of DC specifications are at $T_A = 25\degree C$.
|
All typical values of DC specifications are at $T_A = 25\degree C$.
|
||||||
|
|
||||||
\begin{table}[h]
|
\begin{table}[h!]
|
||||||
\begin{threeparttable}
|
\begin{threeparttable}
|
||||||
\caption{DC Specifications}
|
\caption{DC Specifications}
|
||||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||||
\thickhline
|
\thickhline
|
||||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||||
\textbf{Unit} & \textbf{Conditions} \\
|
\textbf{Unit} & \textbf{Conditions} \\
|
||||||
\hline
|
\hline
|
||||||
Output differential voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
|
Output differential voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
|
||||||
\cline{0-5}
|
\cline{0-5}
|
||||||
$|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
|
$|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
|
||||||
\cline{0-5}
|
\cline{0-5}
|
||||||
Offset voltage & $V_{OS}$ & 1.125 & 1.23 & 1.375 & V & \\
|
Offset voltage & $V_{OS}$ & 1.125 & 1.23 & 1.375 & V & \\
|
||||||
\cline{0-5}
|
\cline{0-5}
|
||||||
$|V_{OS}|$ change (LOW-to-HIGH) & $\Delta V_{OS}$ & & & 25 & mV & \\
|
$|V_{OS}|$ change (LOW-to-HIGH) & $\Delta V_{OS}$ & & & 25 & mV & \\
|
||||||
\hline
|
\hline
|
||||||
Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
|
Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
|
||||||
\hline
|
\hline
|
||||||
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended input voltage \\
|
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended input voltage \\
|
||||||
\thickhline
|
\thickhline
|
||||||
\end{tabularx}
|
\end{tabularx}
|
||||||
\end{threeparttable}
|
\end{threeparttable}
|
||||||
\end{table}
|
\end{table}
|
||||||
|
|
||||||
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
|
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
|
||||||
|
|
||||||
\begin{table}[h]
|
\begin{table}[h!]
|
||||||
\begin{threeparttable}
|
\begin{threeparttable}
|
||||||
\caption{AC Specifications}
|
\caption{AC Specifications}
|
||||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||||
\thickhline
|
\thickhline
|
||||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||||
\textbf{Unit} & \textbf{Conditions} \\
|
\textbf{Unit} & \textbf{Conditions} \\
|
||||||
\hline
|
\hline
|
||||||
Differential output rise time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & Duty cycle = 50\%.\\
|
Differential output rise time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & Duty cycle = 50\%.\\
|
||||||
(20\% to 80\%) & & & & & \\
|
(20\% to 80\%) & & & & & \\
|
||||||
\cline{0-5}
|
\cline{0-5}
|
||||||
Differential output fall time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
|
Differential output fall time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
|
||||||
(80\% to 20\%) & & & & & \\
|
(80\% to 20\%) & & & & & \\
|
||||||
\cline{0-5}
|
\cline{0-5}
|
||||||
Pulse width distortion & & 0.01 & 0.2 & ns & \\
|
Pulse width distortion & & 0.01 & 0.2 & ns & \\
|
||||||
\hline
|
\hline
|
||||||
LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
|
LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
|
||||||
deterministic & & & & & 800 Mbps\\
|
deterministic & & & & & 800 Mbps\\
|
||||||
\hline
|
\hline
|
||||||
LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
|
\end{tabularx}
|
||||||
random (RMS) & & & & & \\
|
\end{threeparttable}
|
||||||
\thickhline
|
\end{table}
|
||||||
\end{tabularx}
|
|
||||||
\end{threeparttable}
|
|
||||||
\end{table}
|
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
|
|
||||||
\section{Configuring IO Direction \& Termination}
|
\begin{table}[h!]
|
||||||
\begin{multicols}{2}
|
\begin{threeparttable}
|
||||||
The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
|
\caption{AC Specifications, cont.}
|
||||||
\begin{itemize}
|
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||||
\itemsep0em
|
\thickhline
|
||||||
\item IO direction switch closed (\texttt{ON}) \\
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
\textbf{Unit} & \textbf{Conditions} \\
|
||||||
\item IO direction switch open (OFF) \\
|
\hline
|
||||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
|
||||||
\end{itemize}
|
random (RMS) & & & & & \\
|
||||||
|
\thickhline
|
||||||
|
\end{tabularx}
|
||||||
|
\end{threeparttable}
|
||||||
|
\end{table}
|
||||||
|
|
||||||
\vspace*{\fill}\columnbreak
|
\section{Configuring IO Direction \& Termination}
|
||||||
\begin{center}
|
|
||||||
\centering
|
\begin{multicols}{2}
|
||||||
\includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
|
|
||||||
\captionof{figure}{Position of switches}
|
The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
|
||||||
\end{center}
|
\begin{itemize}
|
||||||
\end{multicols}
|
\itemsep0em
|
||||||
|
\item IO direction switch closed (\texttt{ON}) \\
|
||||||
|
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||||
|
\item IO direction switch open (OFF) \\
|
||||||
|
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||||
|
\end{itemize}
|
||||||
|
|
||||||
|
\vspace*{\fill}\columnbreak
|
||||||
|
|
||||||
|
\begin{center}
|
||||||
|
\centering
|
||||||
|
\includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
|
||||||
|
\captionof{figure}{Position of switches}
|
||||||
|
\end{center}
|
||||||
|
|
||||||
|
\end{multicols}
|
||||||
|
|
||||||
|
\sysdescsection
|
||||||
|
|
||||||
|
2245 LVDS-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||||
|
|
||||||
|
\begin{tcolorbox}[colback=white]
|
||||||
|
\begin{minted}{json}
|
||||||
|
{
|
||||||
|
"type": "dio",
|
||||||
|
"board": "DIO_LVDS", // optional
|
||||||
|
"ports": [0],
|
||||||
|
"edge_counter": true, // optional
|
||||||
|
"bank_direction_low": "input", // or "output"
|
||||||
|
"bank_direction_high": "output" // or "input"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"type": "dio",
|
||||||
|
"board": "DIO_LVDS",
|
||||||
|
"ports": [1],
|
||||||
|
"bank_direction_low": "output",
|
||||||
|
"bank_direction_high": "output"
|
||||||
|
}
|
||||||
|
\end{minted}
|
||||||
|
\end{tcolorbox}
|
||||||
|
|
||||||
|
Note that due to its high channel account and double EEM connections 2245 LVDS-TTL is entered into a system description as two peripheral entries, each representing two banks.
|
||||||
|
|
||||||
|
The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. Both \texttt{edge\_counter} and IO direction can be specified separately for each entry.
|
||||||
|
|
||||||
|
For single-EEM operation, use only one of two peripheral entries.
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
|
|
||||||
\codesection{2245 LVDS-TTL card}
|
\codesection{2245 LVDS-TTL card}
|
||||||
|
|
||||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||||
|
|
||||||
\subsection{One pulse per second}
|
\subsection{One pulse per second}
|
||||||
The channel should be configured as output in both gateware and hardware.
|
The channel should be configured as output in both gateware and hardware.
|
||||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||||
|
|
||||||
\subsection{Morse code}
|
\subsection{Morse code}
|
||||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
\subsection{Counting rising edges in a 1ms window}
|
|
||||||
The channel should be configured as input in both gateware and hardware.
|
|
||||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
|
||||||
|
|
||||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
\subsection{Counting rising edges in a 1ms window}
|
||||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
The channel should be configured as input in both gateware and hardware.
|
||||||
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||||
|
|
||||||
\subsection{Responding to an external trigger}
|
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||||
One channel needs to be configured as input, and the other as output.
|
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
||||||
|
|
||||||
\newcommand{\wrapspacer}[1]% #1 = special text
|
\subsection{Responding to an external trigger}
|
||||||
{\bgroup
|
One channel needs to be configured as input, and the other as output.
|
||||||
\sbox0{\begin{minipage}{\linewidth}\hrule height0pt
|
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||||
#1\hrule height0pt
|
|
||||||
\end{minipage}}%
|
\newcommand{\wrapspacer}[1]% #1 = special text
|
||||||
\dimen0=\dimexpr \ht0+\dp0\relax
|
{\bgroup
|
||||||
\loop\ifdim\dimen0>\baselineskip
|
\sbox0{\begin{minipage}{\linewidth}\hrule height0pt
|
||||||
\strut\vspace{-\baselineskip}\newline
|
#1\hrule height0pt
|
||||||
\advance\dimen0 by -\baselineskip
|
\end{minipage}}%
|
||||||
\repeat
|
\dimen0=\dimexpr \ht0+\dp0\relax
|
||||||
\noindent\strut\usebox0\par
|
\loop\ifdim\dimen0>\baselineskip
|
||||||
\egroup}
|
\strut\vspace{-\baselineskip}\newline
|
||||||
|
\advance\dimen0 by -\baselineskip
|
||||||
|
\repeat
|
||||||
|
\noindent\strut\usebox0\par
|
||||||
|
\egroup}
|
||||||
|
|
||||||
|
\subsection{SPI Master Device}
|
||||||
|
If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
|
||||||
|
\begin{enumerate}
|
||||||
|
% The config register can be set using set_config.
|
||||||
|
% However, the only difference between these 2 methods is that set_config accepts an arbitrary
|
||||||
|
% frequency, then translate into the rough frequency divisor for set_config_mu.
|
||||||
|
% It doesn't guarantee such frequency would be set as the SPI frequency
|
||||||
|
|
||||||
|
% In addition, finding clock division is quite easy. set_config_mu seems to be a more
|
||||||
|
% straight-forward & representative of the actual implementation.
|
||||||
|
\item Set the \texttt{config} register (e.g. using \texttt{set\char`_config\char`_mu()}).
|
||||||
|
\item Start the SPI transfer by writing the \texttt{data} register using \texttt{write()}.
|
||||||
|
\item If the data from the SPI slave is to be read (i.e. \texttt{SPI\char`_INPUT} was set in \texttt{config}), invoke \texttt{read()} to read.
|
||||||
|
|
||||||
|
\end{enumerate}
|
||||||
|
|
||||||
|
The list of configurations supported in the gateware are listed as below:
|
||||||
|
|
||||||
|
\begin{table}[h]
|
||||||
|
\centering
|
||||||
|
\begin{tabular}{|c|l|}
|
||||||
|
\hline
|
||||||
|
Flag & Description \\ \hline
|
||||||
|
\texttt{SPI\char`_OFFLINE} & Switch all pins to high impedance mode. \\ \hline
|
||||||
|
\texttt{SPI\char`_END} & Next SPI transfer is the last of the transcation. \\ \hline
|
||||||
|
\texttt{SPI\char`_INPUT} & Submit SPI read data as RTIO input event when the transfer is complete. \\ \hline
|
||||||
|
\texttt{SPI\char`_CS\char`_POLARITY} & Active level of chip select (CS) \\ \hline
|
||||||
|
\texttt{SPI\char`_CLK\char`_POLARITY} & Idle level of serial clock (SCK) \\ \hline
|
||||||
|
\texttt{SPI\char`_CLK\char`_PHASE} & Data is sampled on falling edge \& shifted out on rising edge. \\ \hline
|
||||||
|
\texttt{SPI\char`_LSB\char`_FIRST} & LSB is the first on bit on the wire. \\ \hline
|
||||||
|
\texttt{SPI\char`_HALF\char`_DUPLEX} & Use 3-wire SPI, where MOSI is both input \& output capable. \\ \hline
|
||||||
|
\end{tabular}
|
||||||
|
\end{table}
|
||||||
|
|
||||||
|
The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves. The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
\subsection{SPI Master Device}
|
|
||||||
If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
|
|
||||||
\begin{enumerate}
|
|
||||||
% The config register can be set using set_config.
|
|
||||||
% However, the only difference between these 2 methods is that set_config accepts an arbitrary
|
|
||||||
% frequency, then translate into the rough frequency divisor for set_config_mu.
|
|
||||||
% It doesn't guarantee such frequency would be set as the SPI frequency
|
|
||||||
|
|
||||||
% In addition, finding clock division is quite easy. set_config_mu seems to be a more
|
\begin{center}
|
||||||
% straight-forward & representative of the actual implementation.
|
\begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
|
||||||
\item Set the \texttt{config} register (e.g. using \texttt{set\char`_config\char`_mu()}).
|
% SPI master
|
||||||
\item Start the SPI transfer by writing the \texttt{data} register using \texttt{write()}.
|
\draw (0, 1.8) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=2, scale=1] (master) {};
|
||||||
\item If the data from the SPI slave is to be read (i.e. \texttt{SPI\char`_INPUT} was set in \texttt{config}), invoke \texttt{read()} to read.
|
\node [label={center:\large{SPI Master}}] at (-0.6, 2.05) {};
|
||||||
|
\node [label={center:\large{(LVDS-TTL)}}] at (-0.6, 1.55) {};
|
||||||
|
\node [label=left:{SCK}] at (2, 2.8) {};
|
||||||
|
\node [label=left:{MOSI}] at (2, 2.4) {};
|
||||||
|
\node [label=left:{MISO}] at (2, 2.0) {};
|
||||||
|
\node [label=left:{CS0}] at (2, 1.6) {};
|
||||||
|
\node [label=left:{CS1}] at (2, 1.2) {};
|
||||||
|
\node [label=left:{CS2}] at (2, 0.8) {};
|
||||||
|
|
||||||
\end{enumerate}
|
% SPI slaves
|
||||||
|
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||||
|
\draw (7, 2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave0) {};
|
||||||
|
\node [label={center:\large{SPI Slave 0}}] at (7.6, 2.2) {};
|
||||||
|
\node [label=right:{SCK}] at (5, 2.8) {};
|
||||||
|
\node [label=right:{MOSI}] at (5, 2.4) {};
|
||||||
|
\node [label=right:{MISO}] at (5, 2.0) {};
|
||||||
|
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, 1.6) {};
|
||||||
|
|
||||||
The list of configurations supported in the gateware are listed as below:
|
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||||
|
\draw (7, 0) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave1) {};
|
||||||
|
\node [label={center:\large{SPI Slave 1}}] at (7.6, 0) {};
|
||||||
|
\node [label=right:{SCK}] at (5, 0.6) {};
|
||||||
|
\node [label=right:{MOSI}] at (5, 0.2) {};
|
||||||
|
\node [label=right:{MISO}] at (5, -0.2) {};
|
||||||
|
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -0.6) {};
|
||||||
|
|
||||||
\begin{table}[h]
|
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||||
\centering
|
\draw (7, -2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave2) {};
|
||||||
\begin{tabular}{|c|l|}
|
\node [label={center:\large{SPI Slave 2}}] at (7.6, -2.2) {};
|
||||||
\hline
|
\node [label=right:{SCK}] at (5, -1.6) {};
|
||||||
Flag & Description \\ \hline
|
\node [label=right:{MOSI}] at (5, -2.0) {};
|
||||||
\texttt{SPI\char`_OFFLINE} & Switch all pins to high impedance mode. \\ \hline
|
\node [label=right:{MISO}] at (5, -2.4) {};
|
||||||
\texttt{SPI\char`_END} & Next SPI transfer is the last of the transcation. \\ \hline
|
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -2.8) {};
|
||||||
\texttt{SPI\char`_INPUT} & Submit SPI read data as RTIO input event when the transfer is complete. \\ \hline
|
|
||||||
\texttt{SPI\char`_CS\char`_POLARITY} & Active level of chip select (CS) \\ \hline
|
|
||||||
\texttt{SPI\char`_CLK\char`_POLARITY} & Idle level of serial clock (SCK) \\ \hline
|
|
||||||
\texttt{SPI\char`_CLK\char`_PHASE} & Data is sampled on falling edge \& shifted out on rising edge. \\ \hline
|
|
||||||
\texttt{SPI\char`_LSB\char`_FIRST} & LSB is the first on bit on the wire. \\ \hline
|
|
||||||
\texttt{SPI\char`_HALF\char`_DUPLEX} & Use 3-wire SPI, where MOSI is both input \& output capable. \\ \hline
|
|
||||||
\end{tabular}
|
|
||||||
\end{table}
|
|
||||||
|
|
||||||
The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves.
|
% Connect the master to slave 0
|
||||||
The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
|
\draw [-latexslim] (1.95, 2.8) -- (5.05, 2.8);
|
||||||
\begin{center}
|
\draw [-latexslim] (1.95, 2.4) -- (5.05, 2.4);
|
||||||
\begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
|
\draw [latexslim-] (1.95, 2.0) -- (5.05, 2.0);
|
||||||
% SPI master
|
\draw [-latexslim] (1.95, 1.6) -- (5.05, 1.6);
|
||||||
\draw (0, 1.8) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=2, scale=1] (master) {};
|
|
||||||
\node [label={center:\large{SPI Master}}] at (-0.6, 2.05) {};
|
|
||||||
\node [label={center:\large{(LVDS-TTL)}}] at (-0.6, 1.55) {};
|
|
||||||
\node [label=left:{SCK}] at (2, 2.8) {};
|
|
||||||
\node [label=left:{MOSI}] at (2, 2.4) {};
|
|
||||||
\node [label=left:{MISO}] at (2, 2.0) {};
|
|
||||||
\node [label=left:{CS0}] at (2, 1.6) {};
|
|
||||||
\node [label=left:{CS1}] at (2, 1.2) {};
|
|
||||||
\node [label=left:{CS2}] at (2, 0.8) {};
|
|
||||||
|
|
||||||
% SPI slaves
|
% Connect slave 1
|
||||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
\draw [-latexslim] (4.2, 2.8) -- (4.2, 0.6) -- (5.05, 0.6);
|
||||||
\draw (7, 2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave0) {};
|
\draw [-latexslim] (3.8, 2.4) -- (3.8, 0.2) -- (5.05, 0.2);
|
||||||
\node [label={center:\large{SPI Slave 0}}] at (7.6, 2.2) {};
|
\draw [-] (3.4, 2.0) -- (3.4, -0.2) -- (5.05, -0.2);
|
||||||
\node [label=right:{SCK}] at (5, 2.8) {};
|
\draw [-latexslim] (1.95, 1.2) -- (3.0, 1.2) -- (3.0, -0.6) -- (5.05, -0.6);
|
||||||
\node [label=right:{MOSI}] at (5, 2.4) {};
|
|
||||||
\node [label=right:{MISO}] at (5, 2.0) {};
|
|
||||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, 1.6) {};
|
|
||||||
|
|
||||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
% Connect slave 2
|
||||||
\draw (7, 0) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave1) {};
|
\draw [-latexslim] (4.2, 0.6) -- (4.2, -1.6) -- (5.05, -1.6);
|
||||||
\node [label={center:\large{SPI Slave 1}}] at (7.6, 0) {};
|
\draw [-latexslim] (3.8, 0.2) -- (3.8, -2.0) -- (5.05, -2.0);
|
||||||
\node [label=right:{SCK}] at (5, 0.6) {};
|
\draw [-] (3.4, -0.2) -- (3.4, -2.4) -- (5.05, -2.4);
|
||||||
\node [label=right:{MOSI}] at (5, 0.2) {};
|
\draw [-latexslim] (1.95, 0.8) -- (2.6, 0.8) -- (2.6, -2.8) -- (5.05, -2.8);
|
||||||
\node [label=right:{MISO}] at (5, -0.2) {};
|
|
||||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -0.6) {};
|
|
||||||
|
|
||||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
% Add dot to intersection to distinguish from overlaps
|
||||||
\draw (7, -2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave2) {};
|
\node at (4.2, 2.8)[circle,fill,inner sep=0.7pt]{};
|
||||||
\node [label={center:\large{SPI Slave 2}}] at (7.6, -2.2) {};
|
\node at (3.8, 2.4)[circle,fill,inner sep=0.7pt]{};
|
||||||
\node [label=right:{SCK}] at (5, -1.6) {};
|
\node at (3.4, 2.0)[circle,fill,inner sep=0.7pt]{};
|
||||||
\node [label=right:{MOSI}] at (5, -2.0) {};
|
\node at (4.2, 0.6)[circle,fill,inner sep=0.7pt]{};
|
||||||
\node [label=right:{MISO}] at (5, -2.4) {};
|
\node at (3.8, 0.2)[circle,fill,inner sep=0.7pt]{};
|
||||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -2.8) {};
|
\node at (3.4, -0.2)[circle,fill,inner sep=0.7pt]{};
|
||||||
|
|
||||||
% Connect the master to slave 0
|
\end{circuitikz}
|
||||||
\draw [-latexslim] (1.95, 2.8) -- (5.05, 2.8);
|
\end{center}
|
||||||
\draw [-latexslim] (1.95, 2.4) -- (5.05, 2.4);
|
|
||||||
\draw [latexslim-] (1.95, 2.0) -- (5.05, 2.0);
|
|
||||||
\draw [-latexslim] (1.95, 1.6) -- (5.05, 1.6);
|
|
||||||
|
|
||||||
% Connect slave 1
|
\subsubsection{SPI Configuration}
|
||||||
\draw [-latexslim] (4.2, 2.8) -- (4.2, 0.6) -- (5.05, 0.6);
|
The following examples will assume the SPI communication has the following properties:
|
||||||
\draw [-latexslim] (3.8, 2.4) -- (3.8, 0.2) -- (5.05, 0.2);
|
\begin{itemize}
|
||||||
\draw [-] (3.4, 2.0) -- (3.4, -0.2) -- (5.05, -0.2);
|
\item Chip select (CS) is active low
|
||||||
\draw [-latexslim] (1.95, 1.2) -- (3.0, 1.2) -- (3.0, -0.6) -- (5.05, -0.6);
|
\item Serial clock (SCK) idle level is low
|
||||||
|
\item Data is sampled on rising edge of SCK \& shifted out on falling edge of SCK
|
||||||
% Connect slave 2
|
\item Most significant bit (MSB) first
|
||||||
\draw [-latexslim] (4.2, 0.6) -- (4.2, -1.6) -- (5.05, -1.6);
|
\item Full duplex
|
||||||
\draw [-latexslim] (3.8, 0.2) -- (3.8, -2.0) -- (5.05, -2.0);
|
\end{itemize}
|
||||||
\draw [-] (3.4, -0.2) -- (3.4, -2.4) -- (5.05, -2.4);
|
|
||||||
\draw [-latexslim] (1.95, 0.8) -- (2.6, 0.8) -- (2.6, -2.8) -- (5.05, -2.8);
|
|
||||||
|
|
||||||
% Add dot to intersection to distinguish from overlaps
|
|
||||||
\node at (4.2, 2.8)[circle,fill,inner sep=0.7pt]{};
|
|
||||||
\node at (3.8, 2.4)[circle,fill,inner sep=0.7pt]{};
|
|
||||||
\node at (3.4, 2.0)[circle,fill,inner sep=0.7pt]{};
|
|
||||||
\node at (4.2, 0.6)[circle,fill,inner sep=0.7pt]{};
|
|
||||||
\node at (3.8, 0.2)[circle,fill,inner sep=0.7pt]{};
|
|
||||||
\node at (3.4, -0.2)[circle,fill,inner sep=0.7pt]{};
|
|
||||||
|
|
||||||
\end{circuitikz}
|
|
||||||
\end{center}
|
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
\subsubsection{SPI Configuration}
|
|
||||||
The following examples will assume the SPI communication has the following properties:
|
|
||||||
\begin{itemize}
|
|
||||||
\item Chip select (CS) is active low
|
|
||||||
\item Serial clock (SCK) idle level is low
|
|
||||||
\item Data is sampled on rising edge of SCK \& shifted out on falling edge of SCK
|
|
||||||
\item Most significant bit (MSB) first
|
|
||||||
\item Full duplex
|
|
||||||
\end{itemize}
|
|
||||||
The baseline configuration for an \texttt{SPIMaster} instance can be defined as such:
|
|
||||||
\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
|
|
||||||
The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
|
|
||||||
|
|
||||||
\subsubsection{SPI frequency}
|
The baseline configuration for an \texttt{SPIMaster} instance can be defined as such:
|
||||||
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor in [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
|
\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
|
||||||
\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
|
The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
|
||||||
|
|
||||||
\subsubsection{SPI write}
|
\subsubsection{SPI frequency}
|
||||||
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. Suppose the instruction and data are 8 bits and 32 bits respectively. The timing diagram of such a write operation is shown in the following:
|
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor in [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
|
||||||
|
\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
|
||||||
|
|
||||||
\begin{center}
|
\subsubsection{SPI write}
|
||||||
\begin{tikztimingtable}
|
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. Suppose the instruction and data are 8 bits and 32 bits respectively. The timing diagram of such a write operation is shown in the following:
|
||||||
[
|
|
||||||
timing/d/background/.style={fill=white},
|
\begin{center}
|
||||||
timing/lslope=0.2
|
\begin{tikztimingtable}
|
||||||
]
|
[
|
||||||
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
timing/d/background/.style={fill=white},
|
||||||
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
timing/lslope=0.2
|
||||||
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
]
|
||||||
% then print the label from macro. But it turns out tikz-timing will print
|
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
||||||
% the counter value separately, even with an additional macro.
|
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
||||||
% Therefore, it does not work properly.
|
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
||||||
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}, timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
% then print the label from macro. But it turns out tikz-timing will print
|
||||||
UJ{7}8{2I}R{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
% the counter value separately, even with an additional macro.
|
||||||
MOSI & 53U \\
|
% Therefore, it does not work properly.
|
||||||
\end{tikztimingtable}%
|
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}, timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
||||||
\end{center}
|
UJ{7}8{2I}R{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
||||||
|
MOSI & 53U \\
|
||||||
|
\end{tikztimingtable}%
|
||||||
|
\end{center}
|
||||||
|
|
||||||
|
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
|
||||||
|
\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
|
|
||||||
\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
|
|
||||||
|
|
||||||
\subsubsection{SPI read}
|
\subsubsection{SPI read}
|
||||||
A 32-bit read is represented by the following timing diagram:
|
A 32-bit read is represented by the following timing diagram:
|
||||||
|
|
||||||
\begin{center}
|
\begin{center}
|
||||||
\begin{tikztimingtable}
|
\begin{tikztimingtable}
|
||||||
[
|
[
|
||||||
timing/d/background/.style={fill=white},
|
timing/d/background/.style={fill=white},
|
||||||
timing/lslope=0.2
|
timing/lslope=0.2
|
||||||
]
|
]
|
||||||
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
||||||
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
||||||
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
||||||
% then print the label from macro. But it turns out tikz-timing will print
|
% then print the label from macro. But it turns out tikz-timing will print
|
||||||
% the counter value separately, even with an additional macro.
|
% the counter value separately, even with an additional macro.
|
||||||
% Therefore, it does not work properly.
|
% Therefore, it does not work properly.
|
||||||
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}]
|
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}]
|
||||||
UJ{7}8{2I}36U \\
|
UJ{7}8{2I}36U \\
|
||||||
MOSI & [timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
MOSI & [timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
||||||
17UR{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
17UR{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
||||||
\end{tikztimingtable}%
|
\end{tikztimingtable}%
|
||||||
\end{center}
|
\end{center}
|
||||||
|
|
||||||
Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code.
|
Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code.
|
||||||
\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
|
\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
|
||||||
|
|
||||||
\newpage
|
|
||||||
\ordersection{2245 LVDS-TTL}
|
\ordersection{2245 LVDS-TTL}
|
||||||
|
|
||||||
\finalfootnote
|
\finalfootnote
|
||||||
|
|||||||
@ -1,10 +1,10 @@
|
|||||||
\input{preamble.tex}
|
\input{preamble.tex}
|
||||||
\graphicspath{{images/4456-4457}{images}}
|
\graphicspath{{images/4456}{images}}
|
||||||
|
|
||||||
\title{4456 Synthesizer Mirny / 4457 HF Synthesizer Mirny + Almazny}
|
\title{4456 Synthesizer Mirny}
|
||||||
\author{M-Labs Limited}
|
\author{M-Labs Limited}
|
||||||
\date{January 2025}
|
\date{January 2022}
|
||||||
\revision{Revision 2}
|
\revision{Revision 1}
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||||
|
|
||||||
\begin{document}
|
\begin{document}
|
||||||
@ -13,28 +13,29 @@
|
|||||||
\section{Features}
|
\section{Features}
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\item{4-channel VCO/PLL}
|
\item{4-channel VCO/PLL}
|
||||||
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz for 4456 Mirny only}
|
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz}
|
||||||
\item{Up to 13.6 GHz with 4457 mezzanine Almazny}
|
\item{Up to 13.6 GHz with Almazny mezzanine}
|
||||||
\item{Higher frequency resolution than Urukul}
|
\item{Higher frequency resolution than Urukul}
|
||||||
\item{Lower jitter and phase noise}
|
\item{Lower jitter and phase noise}
|
||||||
\item{Large frequency changes take several milliseconds}
|
\item{Large frequency changes take several milliseconds}
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\section{Applications}
|
\section{Applications}
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\item{Low-noise microwave source}
|
\item{Low-noise microwave source}
|
||||||
\item{Quantum state control}
|
\item{Quantum state control}
|
||||||
\item{Driving acousto/electro-optic modulators}
|
\item{Driving acousto/electro-optic modulators}
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\section{General Description}
|
\section{General Description}
|
||||||
The 4456 Synthesizer Mirny card is a 4hp EEM module; the 4457 HF Synthesizer Mirny + Almazny card, consisting of 4456 Mirny plus the 4-channel Almazny HF mezzanine, is a 8hp EEM module. Both Synthesizer cards add microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
The 4456 Synthesizer Mirny card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||||
|
|
||||||
Both cards provide 4 channels of PLL frequency synthesis. 4456 Synthesizer Mirny supports output frequencies from 53 MHz to \textgreater 4GHz. As 4457 HF Synthesizer with Almazny mezzanine this range is expanded up to 13.6 GHz.
|
It provides 4 channels of PLL frequency synthesis. Output frequencies from 53 MHz to \textgreater 4 GHz are supported.The range can be expanded up to 13.6 GHz with the Almazny mezzanine (4467 HF Synthesizer).
|
||||||
|
|
||||||
|
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provides at least 50 dB isolation.
|
||||||
|
|
||||||
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provide at least 50 dB isolation.
|
|
||||||
|
|
||||||
% Switch to next column
|
% Switch to next column
|
||||||
\vfill\break
|
\vfill\break
|
||||||
@ -274,216 +275,158 @@
|
|||||||
|
|
||||||
\begin{figure}[hbt!]
|
\begin{figure}[hbt!]
|
||||||
\centering
|
\centering
|
||||||
\includegraphics[height=2in]{photo4457.jpg}
|
\includegraphics[height=2in]{photo4456.jpg}
|
||||||
\caption{Mirny + Almazny card}
|
\includegraphics[height=3in, angle=90]{Mirny_FP.pdf}
|
||||||
|
\caption{Mirny card and front panel}
|
||||||
\end{figure}
|
\end{figure}
|
||||||
|
|
||||||
% For wide tables, a single column layout is better. It can be switched
|
% For wide tables, a single column layout is better. It can be switched
|
||||||
% page-by-page.
|
% page-by-page.
|
||||||
\onecolumn
|
\onecolumn
|
||||||
|
|
||||||
\begin{figure}[hbt!]
|
\sourcesection{4456 Synthesizer Mirny}{https://github.com/sinara-hw/mirny}
|
||||||
\subfloat[\centering Mirny and Almazny front panels]{{
|
|
||||||
\begin{minipage}[b]{0.5\linewidth}
|
|
||||||
\centering
|
|
||||||
\includegraphics[height=3in, angle=90]{fp4456.pdf} \\
|
|
||||||
\vspace{0.2in}
|
|
||||||
\includegraphics[height=3in, angle=90]{fp4457.pdf}
|
|
||||||
\vspace{0.25in}
|
|
||||||
\end{minipage}
|
|
||||||
}}
|
|
||||||
\subfloat[\centering Mirny, top-down view]{{
|
|
||||||
\includegraphics[height=2.5in]{photo4456.jpg}
|
|
||||||
}}
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
\sourcesectiond{4456 Synthesizer Mirny}{the 4457 Almazny mezzanine}{https://github.com/sinara-hw/mirny}{https://github.com/sinara-hw/Almazny}
|
|
||||||
|
|
||||||
\section{Electrical Specifications}
|
\section{Electrical Specifications}
|
||||||
|
|
||||||
Specifications of parameters are based on the datasheets of the PLL IC
|
Specifications of parameters are based on the datasheets of the PLL IC
|
||||||
(ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}}),
|
(ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}}),
|
||||||
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}}),
|
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}}),
|
||||||
and digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}).
|
and digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}).
|
||||||
Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}\url{https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}}.
|
Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}\url{https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}}.
|
||||||
|
|
||||||
\begin{table}[h]
|
|
||||||
\centering
|
|
||||||
\begin{threeparttable}
|
|
||||||
\caption{Recommended Operating Conditions}
|
|
||||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
|
||||||
\thickhline
|
|
||||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
|
||||||
\textbf{Unit} & \textbf{Conditions} \\
|
|
||||||
\hline
|
|
||||||
% Note to future editors, the clk_div signal in gateware is not used.
|
|
||||||
% Input divider was removed (mirny#8)
|
|
||||||
Clock input & & & & & \\
|
|
||||||
\hspace{3mm}Frequency\repeatfootnote{adf5356}
|
|
||||||
& 10 & & 250 & MHz & Single-ended clock input (PLL config.) \\
|
|
||||||
& 10 & & 600 & MHz & Differential clock input (PLL config.) \\
|
|
||||||
\cline{2-6}
|
|
||||||
\hspace{3mm}Differential input swing\repeatfootnote{clock_buffer}
|
|
||||||
& 0.11 & & 1.55 & V\textsubscript{p-p} & \\
|
|
||||||
\thickhline
|
|
||||||
\end{tabularx}
|
|
||||||
\end{threeparttable}
|
|
||||||
\end{table}
|
|
||||||
|
|
||||||
\begin{table}[h]
|
|
||||||
\centering
|
|
||||||
\begin{threeparttable}
|
|
||||||
\caption{Output Specifications}
|
|
||||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
|
||||||
\thickhline
|
|
||||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
|
||||||
\textbf{Unit} & \textbf{Conditions} \\
|
|
||||||
\hline
|
|
||||||
Frequency & 53.125 & & 4000 & MHz & 4456 Mirny only \\
|
|
||||||
& & & 13600 & MHz & With Almazny mezzanine \\
|
|
||||||
\hline
|
|
||||||
Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
|
|
||||||
\hline
|
|
||||||
\end{tabularx}
|
|
||||||
\end{threeparttable}
|
|
||||||
\end{table}
|
|
||||||
|
|
||||||
\newpage
|
|
||||||
|
|
||||||
\begin{table}[h]
|
\begin{table}[h]
|
||||||
\centering
|
\centering
|
||||||
\begin{threeparttable}
|
\begin{threeparttable}
|
||||||
\caption{Output Specifications, cont.}
|
\caption{Recommended Operating Conditions}
|
||||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||||
\thickhline
|
\thickhline
|
||||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||||
\textbf{Unit} & \textbf{Conditions} \\
|
\textbf{Unit} & \textbf{Conditions} \\
|
||||||
Resolution & & & & \\
|
\hline
|
||||||
\hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{3}{c|}{52} & bits & \\
|
% Note to future editors, the clk_div signal in gateware is not used.
|
||||||
\hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{3}{c|}{24} & bits & \\
|
% Input divider was removed (mirny#8)
|
||||||
\hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{3}{c|}{0.5} & dB & \\
|
Clock input & & & & & \\
|
||||||
\thickhline
|
\hspace{3mm}Frequency\repeatfootnote{adf5356}
|
||||||
\end{tabularx}
|
& 10 & & 250 & MHz & Single-ended clock input (PLL config.) \\
|
||||||
\end{threeparttable}
|
& 10 & & 600 & MHz & Differential clock input (PLL config.) \\
|
||||||
\end{table}
|
\cline{2-6}
|
||||||
|
\hspace{3mm}Differential input swing\repeatfootnote{clock_buffer}
|
||||||
|
& 0.11 & & 1.55 & V\textsubscript{p-p} & \\
|
||||||
|
\thickhline
|
||||||
|
\end{tabularx}
|
||||||
|
\end{threeparttable}
|
||||||
|
\end{table}
|
||||||
|
|
||||||
Phase noise performance of 4456 Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. 4456 Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
|
\begin{table}[h]
|
||||||
|
\centering
|
||||||
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
|
\begin{threeparttable}
|
||||||
|
\caption{Output Specifications}
|
||||||
\begin{figure}[H]
|
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||||
\centering
|
\thickhline
|
||||||
\includegraphics[height=3in]{mirny_phase_noise_cm_choke.png}
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||||
\caption{Phase noise measurement at 1 GHz}
|
\textbf{Unit} & \textbf{Conditions} \\
|
||||||
\end{figure}
|
\hline
|
||||||
|
Frequency & 53.125 & & 4000 & MHz & \\
|
||||||
\begin{itemize}
|
\hline
|
||||||
\item Red: Before any modifications
|
Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
|
||||||
\item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
|
\hline
|
||||||
\end{itemize}
|
Resolution & \multicolumn{4}{c|}{} & \\
|
||||||
|
\hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{4}{c|}{52 bits} & \\
|
||||||
|
\hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{4}{c|}{24 bits} & \\
|
||||||
|
\hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{4}{c|}{0.5 dB} & \\
|
||||||
|
\thickhline
|
||||||
|
\end{tabularx}
|
||||||
|
\end{threeparttable}
|
||||||
|
\end{table}
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
|
|
||||||
Phase noise at different output frequencies is then measured:
|
Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
|
||||||
|
|
||||||
\newcolumntype{Y}{>{\centering\arraybackslash}X}
|
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
|
||||||
|
\begin{itemize}
|
||||||
|
\item Red: Before any modifications
|
||||||
|
\item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
|
||||||
|
\end{itemize}
|
||||||
|
|
||||||
\begin{table}[hbt!]
|
\begin{figure}[H]
|
||||||
\centering
|
\centering
|
||||||
\begin{threeparttable}
|
\includegraphics[height=3in]{mirny_phase_noise_cm_choke.png}
|
||||||
\caption{Phase noise performance}
|
\caption{Phase noise measurement at 1 GHz}
|
||||||
\begin{tabularx}{0.8\textwidth}{| c | Y | Y | Y | Y | Y |}
|
\end{figure}
|
||||||
\thickhline
|
|
||||||
\multirow{2}{*}{\textbf{Output frequency}} &
|
|
||||||
\multicolumn{5}{c|}{\textbf{Phase noise (dBc/Hz) at carrier offset}}\\
|
|
||||||
\cline{2-6} & 1 kHz & 10 kHz & 100 kHz & 1 MHz & 10 MHz \\
|
|
||||||
\hline
|
|
||||||
125 MHz & -114 & -116 & -115 & -132 & -133 \\
|
|
||||||
\hline
|
|
||||||
500 MHz & -107 & -129 & -111 & -130 & -132 \\
|
|
||||||
\hline
|
|
||||||
1 GHz & -102 & -106 & -107 & -125 & -133 \\
|
|
||||||
\hline
|
|
||||||
2 GHz & -102 & -98 & -104 & -123 & -124 \\
|
|
||||||
\hline
|
|
||||||
3.5 GHz & -96 & -101 & -103 & -127 & -128 \\
|
|
||||||
\thickhline
|
|
||||||
\end{tabularx}
|
|
||||||
\end{threeparttable}
|
|
||||||
\end{table}
|
|
||||||
|
|
||||||
\begin{figure}[H]
|
Phase noise at different output frequencies is then measured:
|
||||||
\centering
|
|
||||||
\includegraphics[height=3in]{mirny_phase_noise_frequency.png}
|
\newcolumntype{Y}{>{\centering\arraybackslash}X}
|
||||||
\caption{Phase noise measurement}
|
|
||||||
\end{figure}
|
\begin{table}[hbt!]
|
||||||
|
\centering
|
||||||
|
\begin{threeparttable}
|
||||||
|
\caption{Phase noise performance}
|
||||||
|
\begin{tabularx}{0.8\textwidth}{| c | Y | Y | Y | Y | Y |}
|
||||||
|
\thickhline
|
||||||
|
\multirow{2}{*}{\textbf{Output frequency}} &
|
||||||
|
\multicolumn{5}{c|}{\textbf{Phase noise (dBc/Hz) at carrier offset}}\\
|
||||||
|
\cline{2-6} & 1 kHz & 10 kHz & 100 kHz & 1 MHz & 10 MHz \\
|
||||||
|
\hline
|
||||||
|
125 MHz & -114 & -116 & -115 & -132 & -133 \\
|
||||||
|
\hline
|
||||||
|
500 MHz & -107 & -129 & -111 & -130 & -132 \\
|
||||||
|
\hline
|
||||||
|
1 GHz & -102 & -106 & -107 & -125 & -133 \\
|
||||||
|
\hline
|
||||||
|
2 GHz & -102 & -98 & -104 & -123 & -124 \\
|
||||||
|
\hline
|
||||||
|
3.5 GHz & -96 & -101 & -103 & -127 & -128 \\
|
||||||
|
\thickhline
|
||||||
|
\end{tabularx}
|
||||||
|
\end{threeparttable}
|
||||||
|
\end{table}
|
||||||
|
|
||||||
\newpage
|
\newpage
|
||||||
\sysdescsection
|
|
||||||
|
|
||||||
4456 Synthesizer Mirny must be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
\begin{figure}[H]
|
||||||
|
\centering
|
||||||
\begin{tcolorbox}[colback=white]
|
\includegraphics[height=3in]{mirny_phase_noise_frequency.png}
|
||||||
\begin{minted}{json}
|
\caption{Phase noise measurement}
|
||||||
{
|
\end{figure}
|
||||||
"type": "mirny",
|
|
||||||
"ports": 0,
|
|
||||||
"clk_sel": "mmcx", // optional
|
|
||||||
"refclk": 125e6 // optional
|
|
||||||
}
|
|
||||||
\end{minted}
|
|
||||||
\end{tcolorbox}
|
|
||||||
|
|
||||||
Replace 0 with the EEM port number used on the core device. Any port can be used. The \texttt{clk\_sel} field is optional and may be specified as one of either \texttt{xo}, \texttt{mmcx}, or \texttt{sma}. The default is \texttt{xo}. The \texttt{refclk} field is optional and the default is \texttt{100e6}.
|
|
||||||
|
|
||||||
For 4457 Mirny + Almazny, one field must be added:
|
|
||||||
|
|
||||||
\begin{tcolorbox}[colback=white]
|
|
||||||
\begin{minted}{json}
|
|
||||||
{
|
|
||||||
"type": "mirny",
|
|
||||||
"almazny": true,
|
|
||||||
"ports": 0
|
|
||||||
}
|
|
||||||
\end{minted}
|
|
||||||
\end{tcolorbox}
|
|
||||||
|
|
||||||
\codesection{4456 Synthesizer Mirny}
|
\codesection{4456 Synthesizer Mirny}
|
||||||
|
|
||||||
\subsection{1 GHz sinusoidal wave}
|
\subsection{1 GHz sinusoidal wave}
|
||||||
Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.
|
Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.
|
||||||
|
|
||||||
\inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
|
\inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
|
||||||
|
|
||||||
\subsection{ADF5356 power control}
|
\subsection{ADF5356 power control}
|
||||||
Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:
|
Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:
|
||||||
|
|
||||||
\inputcolorboxminted{firstline=28,lastline=28}{examples/pll.py}
|
\inputcolorboxminted{firstline=28,lastline=28}{examples/pll.py}
|
||||||
|
|
||||||
The parameter corresponds to a specific change of output power according to the following table\repeatfootnote{adf5356}.
|
The parameter corresponds to a specific change of output power according to the following table\repeatfootnote{adf5356}.
|
||||||
|
|
||||||
\begin{center}
|
\begin{center}
|
||||||
\captionof{table}{Power changes from ADF5356}
|
\captionof{table}{Power changes from ADF5356}
|
||||||
\begin{tabular}{|c|c|}
|
\begin{tabular}{|c|c|}
|
||||||
\hline
|
\hline
|
||||||
Parameter & Power \\ \hline
|
Parameter & Power \\ \hline
|
||||||
0 & -4 dBm \\ \hline
|
0 & -4 dBm \\ \hline
|
||||||
1 & -1 dBm \\ \hline
|
1 & -1 dBm \\ \hline
|
||||||
2 & +2 dBm \\ \hline
|
2 & +2 dBm \\ \hline
|
||||||
3 & +5 dBm \\ \hline
|
3 & +5 dBm \\ \hline
|
||||||
\end{tabular}
|
\end{tabular}
|
||||||
\end{center}
|
\end{center}
|
||||||
|
|
||||||
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the following line"
|
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the following line"
|
||||||
|
|
||||||
\inputcolorboxminted{firstline=29,lastline=29}{examples/pll.py}
|
\inputcolorboxminted{firstline=29,lastline=29}{examples/pll.py}
|
||||||
|
|
||||||
\subsection{Periodic 100\textmu s pulses}
|
\subsection{Periodic 100\textmu s pulses}
|
||||||
The output can be toggled on and off periodically using the RF switches. The following code emits a 100\textmu s pulse in every millisecond. A microwave signal should be programmed in prior (such as the 1 GHz wave example).
|
The output can be toggled on and off periodically using the RF switches. The following code emits a 100\textmu s pulse in every millisecond. A microwave signal should be programmed in prior (such as the 1 GHz wave example).
|
||||||
|
|
||||||
\inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
|
\inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
|
||||||
|
|
||||||
\ordersection{4456 Synthesizer Mirny or 4457 HF Synthesizer Mirny + Almazny}
|
\ordersection{4456 Synthesizer Mirny}
|
||||||
|
|
||||||
\finalfootnote
|
\finalfootnote
|
||||||
|
|
||||||
64
4459.tex
64
4459.tex
@ -1,64 +0,0 @@
|
|||||||
\input{preamble.tex}
|
|
||||||
\graphicspath{{images/4459}, {images}}
|
|
||||||
|
|
||||||
\title{4459 PDH Lock Generator Pounder}
|
|
||||||
\author{M-Labs Limited}
|
|
||||||
\date{January 2025}
|
|
||||||
\revision{Revision 0}
|
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
|
||||||
|
|
||||||
\begin{document}
|
|
||||||
|
|
||||||
\maketitle
|
|
||||||
|
|
||||||
\section{Features}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{features}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{Applications}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{applications}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{General Description}
|
|
||||||
|
|
||||||
% Switch to next column
|
|
||||||
\vfill\break
|
|
||||||
|
|
||||||
%\begin{figure}[h]
|
|
||||||
% \centering
|
|
||||||
% \scalebox{1.15}{
|
|
||||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
|
||||||
% \begin{scope}[]
|
|
||||||
% % if applicable
|
|
||||||
% \end{scope}
|
|
||||||
% \end{circuitikz}
|
|
||||||
% }
|
|
||||||
|
|
||||||
% \caption{Simplified Block Diagram}
|
|
||||||
%\end{figure}
|
|
||||||
|
|
||||||
\begin{figure}[hbt!]
|
|
||||||
\centering
|
|
||||||
\includegraphics[height=2.5in]{photo4459.jpg}
|
|
||||||
\caption{Pounder + Stabilizer cards}
|
|
||||||
\includegraphics[height=3in, angle=90]{fp4459.pdf}
|
|
||||||
\caption{Pounder + Stabilizer front panel}
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
% For wide tables, a single column layout is better. It can be switched
|
|
||||||
% page-by-page.
|
|
||||||
\onecolumn
|
|
||||||
|
|
||||||
\sourcesectiond{4459 PDH Lock Generator Pounder}{Stabilizer}{https://github.com/sinara-hw/Pounder}{https://github.com/sinara-hw/Stabilizer}
|
|
||||||
|
|
||||||
\section{Specifications}
|
|
||||||
|
|
||||||
\ordersection{4459 Pounder + Stabilizer}
|
|
||||||
|
|
||||||
\finalfootnote
|
|
||||||
|
|
||||||
\end{document}
|
|
||||||
63
4624.tex
63
4624.tex
@ -1,63 +0,0 @@
|
|||||||
\input{preamble.tex}
|
|
||||||
\graphicspath{{images}}
|
|
||||||
|
|
||||||
\title{4624 AWG Phaser}
|
|
||||||
\author{M-Labs Limited}
|
|
||||||
\date{December 2024}
|
|
||||||
\revision{Revision 0}
|
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
|
||||||
|
|
||||||
\begin{document}
|
|
||||||
\maketitle
|
|
||||||
|
|
||||||
\section{Features}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{features}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{Applications}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{applications}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{General Description}
|
|
||||||
|
|
||||||
% Switch to next column
|
|
||||||
\vfill\break
|
|
||||||
|
|
||||||
\begin{figure}[h]
|
|
||||||
\centering
|
|
||||||
\scalebox{1.15}{
|
|
||||||
\begin{circuitikz}[european, every label/.append style={align=center}]
|
|
||||||
\begin{scope}[]
|
|
||||||
% if applicable
|
|
||||||
\end{scope}
|
|
||||||
\end{circuitikz}
|
|
||||||
}
|
|
||||||
|
|
||||||
\caption{Simplified Block Diagram}
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
\begin{figure}[hbt!]
|
|
||||||
\centering
|
|
||||||
% card photo
|
|
||||||
% front panel
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
% For wide tables, a single column layout is better. It can be switched
|
|
||||||
% page-by-page.
|
|
||||||
\onecolumn
|
|
||||||
|
|
||||||
\section{Specifications}
|
|
||||||
|
|
||||||
\newpage
|
|
||||||
|
|
||||||
\section{Example ARTIQ code}
|
|
||||||
\section*{}
|
|
||||||
\vspace*{\fill}
|
|
||||||
|
|
||||||
\finalfootnote
|
|
||||||
|
|
||||||
\end{document}
|
|
||||||
89
5538.tex
89
5538.tex
@ -1,89 +0,0 @@
|
|||||||
\input{preamble.tex}
|
|
||||||
\graphicspath{{images/5538}{images}}
|
|
||||||
|
|
||||||
\title{5538 MCX-TTL}
|
|
||||||
\author{M-Labs Limited}
|
|
||||||
\date{January 2025}
|
|
||||||
\revision{Revision 0}
|
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
|
||||||
|
|
||||||
\begin{document}
|
|
||||||
\maketitle
|
|
||||||
|
|
||||||
\section{Features}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{32 channels}
|
|
||||||
\item{Internal IDC connector}
|
|
||||||
\item{External MCX connectors}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{Applications}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{Break out analog signals}
|
|
||||||
\item{MCX adapter for: \begin{itemize}
|
|
||||||
\item{5432 DAC Zotino}
|
|
||||||
\item{5632 DAC Fastino}
|
|
||||||
\end{itemize}}
|
|
||||||
\item{Convert from/to HD68 with 5568 HD68-IDC}
|
|
||||||
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{General Description}
|
|
||||||
The 5538 MCX-IDC card is a 8hp EEM Module, part of the ARTIQ/Sinara family. It is capable of breaking out analog signals from IDC connectors to MCX connectors. IDC connectors can be found on 5432 DAC Zotino, 5632 DAC Fastino and 5568 HD68-IDC.
|
|
||||||
|
|
||||||
One card provides 32 channels, enough to break out all channels of 5432 DAC Zotino, 5632 DAC Fastino or 5568 HD68-IDC.
|
|
||||||
|
|
||||||
% Switch to next column
|
|
||||||
\vfill\break
|
|
||||||
%\begin{figure}[h]
|
|
||||||
% \centering
|
|
||||||
% \scalebox{1.15}{
|
|
||||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
|
||||||
% \begin{scope}[]
|
|
||||||
% % if applicable
|
|
||||||
% \end{scope}
|
|
||||||
% \end{circuitikz}
|
|
||||||
% }
|
|
||||||
|
|
||||||
% \caption{Simplified Block Diagram}
|
|
||||||
%\end{figure}
|
|
||||||
|
|
||||||
\begin{figure}[hbt!]
|
|
||||||
\centering
|
|
||||||
%\includegraphics[height=2.5in]{photo5538.jpg}
|
|
||||||
\caption{MCX-IDC card}
|
|
||||||
%\includegraphics[height=2.5in, angle=90]{fp5538.pdf}
|
|
||||||
\caption{MCX-IDC front panel}
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
% For wide tables, a single column layout is better. It can be switched
|
|
||||||
% page-by-page.
|
|
||||||
\onecolumn
|
|
||||||
|
|
||||||
\sourcesection{5538 MCX-IDC}{https://github.com/sinara-hw/IDC_MCX_Adapter}
|
|
||||||
|
|
||||||
\section{Electrical Specifications}
|
|
||||||
|
|
||||||
\begin{table}[h]
|
|
||||||
\centering
|
|
||||||
\begin{threeparttable}
|
|
||||||
\caption{Electrical Specifications}
|
|
||||||
\begin{tabularx}{0.65\textwidth}{l | c | c | X}
|
|
||||||
\thickhline
|
|
||||||
\textbf{Parameter} & \textbf{Max. Value} & \textbf{Unit} & \textbf{Conditions} \\
|
|
||||||
\thickhline
|
|
||||||
\end{tabularx}
|
|
||||||
\end{threeparttable}
|
|
||||||
\end{table}
|
|
||||||
|
|
||||||
\section{Channel Mapping}
|
|
||||||
|
|
||||||
% ?
|
|
||||||
|
|
||||||
\ordersection{5538 MCX-IDC}
|
|
||||||
|
|
||||||
\finalfootnote
|
|
||||||
|
|
||||||
\end{document}
|
|
||||||
63
5632.tex
63
5632.tex
@ -1,63 +0,0 @@
|
|||||||
\input{preamble.tex}
|
|
||||||
\graphicspath{{images/5632}, {images}}
|
|
||||||
|
|
||||||
\title{5632 DAC Fastino}
|
|
||||||
\author{M-Labs Limited}
|
|
||||||
\date{January 2025}
|
|
||||||
\revision{Revision 0}
|
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
|
||||||
|
|
||||||
\begin{document}
|
|
||||||
\maketitle
|
|
||||||
|
|
||||||
\section{Features}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{features}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{Applications}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{applications}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{General Description}
|
|
||||||
|
|
||||||
% Switch to next column
|
|
||||||
\vfill\break
|
|
||||||
|
|
||||||
%\begin{figure}[h]
|
|
||||||
% \centering
|
|
||||||
% \scalebox{1.15}{
|
|
||||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
|
||||||
% \begin{scope}[]
|
|
||||||
% % if applicable
|
|
||||||
% \end{scope}
|
|
||||||
% \end{circuitikz}
|
|
||||||
% }
|
|
||||||
|
|
||||||
% \caption{Simplified Block Diagram}
|
|
||||||
%\end{figure}
|
|
||||||
|
|
||||||
\begin{figure}[hbt!]
|
|
||||||
\centering
|
|
||||||
\includegraphics[height=2.25in]{photo5632.jpg}
|
|
||||||
\caption{Fastino card}
|
|
||||||
\includegraphics[height=3in, angle=90]{fp5632.pdf}
|
|
||||||
\caption{Fastino front panel}
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
% For wide tables, a single column layout is better. It can be switched
|
|
||||||
% page-by-page.
|
|
||||||
\onecolumn
|
|
||||||
|
|
||||||
\sourcesection{5632 DAC Fastino}{https://github.com/sinara-hw/Fastino}
|
|
||||||
|
|
||||||
\section{Specifications}
|
|
||||||
|
|
||||||
\ordersection{5632 DAC Fastino}
|
|
||||||
|
|
||||||
\finalfootnote
|
|
||||||
|
|
||||||
\end{document}
|
|
||||||
63
5633.tex
63
5633.tex
@ -1,63 +0,0 @@
|
|||||||
\input{preamble.tex}
|
|
||||||
\graphicspath{{images/5633}, {images}}
|
|
||||||
|
|
||||||
\title{5633 HV Amplifier}
|
|
||||||
\author{M-Labs Limited}
|
|
||||||
\date{January 2025}
|
|
||||||
\revision{Revision 0}
|
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
|
||||||
|
|
||||||
\begin{document}
|
|
||||||
\maketitle
|
|
||||||
|
|
||||||
\section{Features}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{features}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{Applications}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{applications}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{General Description}
|
|
||||||
|
|
||||||
% Switch to next column
|
|
||||||
\vfill\break
|
|
||||||
|
|
||||||
%\begin{figure}[h]
|
|
||||||
% \centering
|
|
||||||
% \scalebox{1.15}{
|
|
||||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
|
||||||
% \begin{scope}[]
|
|
||||||
% % if applicable
|
|
||||||
% \end{scope}
|
|
||||||
% \end{circuitikz}
|
|
||||||
% }
|
|
||||||
|
|
||||||
% \caption{Simplified Block Diagram}
|
|
||||||
%\end{figure}
|
|
||||||
|
|
||||||
\begin{figure}[hbt!]
|
|
||||||
\centering
|
|
||||||
\includegraphics[height=2.25in]{photo5633.jpg}
|
|
||||||
\caption{HV Amplifier card}
|
|
||||||
\includegraphics[height=3in, angle=90]{fp5633.pdf}
|
|
||||||
\caption{HV Amplifier front panel}
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
% For wide tables, a single column layout is better. It can be switched
|
|
||||||
% page-by-page.
|
|
||||||
\onecolumn
|
|
||||||
|
|
||||||
\sourcesection{5633 HV Amplifier}{https://github.com/sinara-hw/HVAMP_32}
|
|
||||||
|
|
||||||
\section{Specifications}
|
|
||||||
|
|
||||||
\ordersection{5633 HV Amplifier}
|
|
||||||
|
|
||||||
\finalfootnote
|
|
||||||
|
|
||||||
\end{document}
|
|
||||||
63
6302.tex
63
6302.tex
@ -1,63 +0,0 @@
|
|||||||
\input{preamble.tex}
|
|
||||||
\graphicspath{{images/6302}, {images}}
|
|
||||||
|
|
||||||
\title{6302 Grabber}
|
|
||||||
\author{M-Labs Limited}
|
|
||||||
\date{January 2025}
|
|
||||||
\revision{Revision 0}
|
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
|
||||||
|
|
||||||
\begin{document}
|
|
||||||
\maketitle
|
|
||||||
|
|
||||||
\section{Features}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{features}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{Applications}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{applications}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{General Description}
|
|
||||||
|
|
||||||
% Switch to next column
|
|
||||||
\vfill\break
|
|
||||||
|
|
||||||
%\begin{figure}[h]
|
|
||||||
% \centering
|
|
||||||
% \scalebox{1.15}{
|
|
||||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
|
||||||
% \begin{scope}[]
|
|
||||||
% % if applicable
|
|
||||||
% \end{scope}
|
|
||||||
% \end{circuitikz}
|
|
||||||
% }
|
|
||||||
|
|
||||||
% \caption{Simplified Block Diagram}
|
|
||||||
%\end{figure}
|
|
||||||
|
|
||||||
\begin{figure}[hbt!]
|
|
||||||
\centering
|
|
||||||
\includegraphics[height=3in, angle=90]{photo6302.jpg}
|
|
||||||
\caption{Grabber card}
|
|
||||||
\includegraphics[height=3in, angle=90]{fp6302.pdf}
|
|
||||||
\caption{Grabber front panel}
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
% For wide tables, a single column layout is better. It can be switched
|
|
||||||
% page-by-page.
|
|
||||||
\onecolumn
|
|
||||||
|
|
||||||
\sourcesection{6302 Grabber}{https://github.com/sinara-hw/Grabber}
|
|
||||||
|
|
||||||
\section{Specifications}
|
|
||||||
|
|
||||||
\ordersection{6302 Grabber}
|
|
||||||
|
|
||||||
\finalfootnote
|
|
||||||
|
|
||||||
\end{document}
|
|
||||||
@ -1,66 +0,0 @@
|
|||||||
\input{preamble.tex}
|
|
||||||
\graphicspath{{images/8451-8453}, {images}}
|
|
||||||
|
|
||||||
\title{8451 Thermostat / 8453 Thermostat EEM}
|
|
||||||
\author{M-Labs Limited}
|
|
||||||
\date{January 2025}
|
|
||||||
\revision{Revision 0}
|
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
|
||||||
|
|
||||||
\begin{document}
|
|
||||||
\maketitle
|
|
||||||
|
|
||||||
\section{Features}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{features}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{Applications}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{applications}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{General Description}
|
|
||||||
|
|
||||||
% Switch to next column
|
|
||||||
\vfill\break
|
|
||||||
|
|
||||||
%\begin{figure}[h]
|
|
||||||
% \centering
|
|
||||||
% \scalebox{1.15}{
|
|
||||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
|
||||||
% \begin{scope}[]
|
|
||||||
% % if applicable
|
|
||||||
% \end{scope}
|
|
||||||
% \end{circuitikz}
|
|
||||||
% }
|
|
||||||
|
|
||||||
% \caption{Simplified Block Diagram}
|
|
||||||
%\end{figure}
|
|
||||||
|
|
||||||
\begin{figure}[hbt!]
|
|
||||||
\centering
|
|
||||||
\includegraphics[height=2in]{photo8451.jpg}
|
|
||||||
\caption{Thermostat}
|
|
||||||
\includegraphics[height=2in]{photo8453.jpg}
|
|
||||||
\caption{Thermostat EEM}
|
|
||||||
\includegraphics[angle=90, height=0.6in]{fp8453.pdf}
|
|
||||||
\caption{Thermostat EEM front panel}%
|
|
||||||
\label{fig:example}%
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
% For wide tables, a single column layout is better. It can be switched
|
|
||||||
% page-by-page.
|
|
||||||
\onecolumn
|
|
||||||
|
|
||||||
\sourcesectiond{8451 Thermostat}{8453 Thermostat EEM}{https://github.com/sinara-hw/Thermostat}{https://github.com/sinara-hw/Thermostat_EEM}
|
|
||||||
|
|
||||||
\section{Specifications}
|
|
||||||
|
|
||||||
\ordersection{8451 Thermostat or 8453 Thermostat EEM}
|
|
||||||
|
|
||||||
\finalfootnote
|
|
||||||
|
|
||||||
\end{document}
|
|
||||||
@ -1,66 +0,0 @@
|
|||||||
\input{preamble.tex}
|
|
||||||
\graphicspath{{images/8452-8462}, {images}}
|
|
||||||
|
|
||||||
\title{8452 DSP Stabilizer / 8462 DSP Fast Servo}
|
|
||||||
\author{M-Labs Limited}
|
|
||||||
\date{January 2025}
|
|
||||||
\revision{Revision 0}
|
|
||||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
|
||||||
|
|
||||||
\begin{document}
|
|
||||||
\maketitle
|
|
||||||
|
|
||||||
\section{Features}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{features}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{Applications}
|
|
||||||
|
|
||||||
\begin{itemize}
|
|
||||||
\item{applications}
|
|
||||||
\end{itemize}
|
|
||||||
|
|
||||||
\section{General Description}
|
|
||||||
|
|
||||||
% Switch to next column
|
|
||||||
\vfill\break
|
|
||||||
|
|
||||||
%\begin{figure}[h]
|
|
||||||
% \centering
|
|
||||||
% \scalebox{1.15}{
|
|
||||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
|
||||||
% \begin{scope}[]
|
|
||||||
% % if applicable
|
|
||||||
% \end{scope}
|
|
||||||
% \end{circuitikz}
|
|
||||||
% }
|
|
||||||
|
|
||||||
% \caption{Simplified Block Diagram}
|
|
||||||
%\end{figure}
|
|
||||||
|
|
||||||
\begin{figure}[hbt!]
|
|
||||||
\centering
|
|
||||||
\includegraphics[height=2in]{photo8452.jpg}
|
|
||||||
\caption{Stabilizer card, top view}
|
|
||||||
\includegraphics[height=2in]{photo8462.jpg}
|
|
||||||
\caption{Fast Servo card, side view}
|
|
||||||
\includegraphics[height=3in, angle=90]{fp8452.pdf}
|
|
||||||
\includegraphics[height=3in, angle=90]{fp8462.pdf}
|
|
||||||
\caption{Stabilizer and Fast Servo front panels}
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
% For wide tables, a single column layout is better. It can be switched
|
|
||||||
% page-by-page.
|
|
||||||
\onecolumn
|
|
||||||
|
|
||||||
\sourcesectiond{8452 DSP Stabilizer}{8462 DSP Fast Servo}{https://github.com/sinara-hw/Stabilizer}{https://github.com/sinara-hw/Fast_Servo}
|
|
||||||
|
|
||||||
\section{Specifications}
|
|
||||||
|
|
||||||
\ordersection{8452 DSP Stabilizer or 8462 DSP Fast Servo}
|
|
||||||
|
|
||||||
\finalfootnote
|
|
||||||
|
|
||||||
\end{document}
|
|
||||||
2
Makefile
2
Makefile
@ -1,4 +1,4 @@
|
|||||||
inputs = 1008 1106 1124 1550 2118-2128 2238 2245 4410-4412 4456-4457 4459 4624 5108 5432 5632 5633 5518-5528 5538 5568 6302 7210 8451-8453 8452-8462
|
inputs = 1124 1125 2118-2128 2238 2245 4410-4412 4456 5108 5432 5518-5528 5568 7210
|
||||||
dir = build
|
dir = build
|
||||||
|
|
||||||
all: $(inputs)
|
all: $(inputs)
|
||||||
|
|||||||
99
examples/unsorted
Normal file
99
examples/unsorted
Normal file
@ -0,0 +1,99 @@
|
|||||||
|
from artiq.experiment import *
|
||||||
|
|
||||||
|
class SineWave(EnvExperiment):
|
||||||
|
def build(self):
|
||||||
|
self.setattr_device("core")
|
||||||
|
|
||||||
|
self.leds = dict()
|
||||||
|
self.ttl_outs = dict()
|
||||||
|
|
||||||
|
self.dacs_config = dict()
|
||||||
|
self.dac_volt = dict()
|
||||||
|
self.dac_dds = dict()
|
||||||
|
self.dac_trigger = dict()
|
||||||
|
|
||||||
|
ddb = self.get_device_db()
|
||||||
|
for name, desc in ddb.items():
|
||||||
|
if isinstance(desc, dict) and desc["type"] == "local":
|
||||||
|
module, cls = desc["module"], desc["class"]
|
||||||
|
if (module, cls) == ("artiq.coredevice.ttl", "TTLOut"):
|
||||||
|
dev = self.get_device(name)
|
||||||
|
if "led" in name:
|
||||||
|
self.leds[name] = dev
|
||||||
|
else:
|
||||||
|
self.ttl_outs[name] = dev
|
||||||
|
|
||||||
|
if (module, cls) == ("artiq.coredevice.shuttler", "Config"):
|
||||||
|
dev = self.get_device(name)
|
||||||
|
self.dacs_config[name] = dev
|
||||||
|
|
||||||
|
if (module, cls) == ("artiq.coredevice.shuttler", "Volt"):
|
||||||
|
dev = self.get_device(name)
|
||||||
|
self.dac_volt[name] = dev
|
||||||
|
|
||||||
|
if (module, cls) == ("artiq.coredevice.shuttler", "Dds"):
|
||||||
|
dev = self.get_device(name)
|
||||||
|
self.dac_dds[name] = dev
|
||||||
|
|
||||||
|
if (module, cls) == ("artiq.coredevice.shuttler", "Trigger"):
|
||||||
|
dev = self.get_device(name)
|
||||||
|
self.dac_trigger[name] = dev
|
||||||
|
|
||||||
|
|
||||||
|
self.leds = sorted(self.leds.items(), key=lambda x: x[1].channel)
|
||||||
|
self.ttl_outs = sorted(self.ttl_outs.items(), key=lambda x: x[1].channel)
|
||||||
|
|
||||||
|
self.dacs_config = sorted(self.dacs_config.items(), key=lambda x: x[1].channel)
|
||||||
|
self.dac_volt = sorted(self.dac_volt.items(), key=lambda x: x[1].channel)
|
||||||
|
self.dac_dds = sorted(self.dac_dds.items(), key=lambda x: x[1].channel)
|
||||||
|
self.dac_trigger = sorted(self.dac_trigger.items(), key=lambda x: x[1].channel)
|
||||||
|
|
||||||
|
|
||||||
|
@kernel
|
||||||
|
def set_dac_config(self, config):
|
||||||
|
config.set_config(0xFFFF)
|
||||||
|
|
||||||
|
@kernel
|
||||||
|
def set_test_dac_volt(self, volt):
|
||||||
|
a0 = 0
|
||||||
|
a1 = 0
|
||||||
|
a2 = 0
|
||||||
|
a3 = 0
|
||||||
|
volt.set_waveform(a0, a1, a2, a3)
|
||||||
|
|
||||||
|
|
||||||
|
@kernel
|
||||||
|
def set_test_dac_dds(self, dds):
|
||||||
|
b0 = 0x0FFF
|
||||||
|
b1 = 0
|
||||||
|
b2 = 0
|
||||||
|
b3 = 0
|
||||||
|
c0 = 0
|
||||||
|
c1 = 0x147AE148 # Frequency = 10MHz
|
||||||
|
c2 = 0
|
||||||
|
dds.set_waveform(b0, b1, b2, b3, c0, c1, c2)
|
||||||
|
|
||||||
|
@kernel
|
||||||
|
def set_dac_trigger(self, trigger):
|
||||||
|
trigger.trigger(0xFFFF)
|
||||||
|
|
||||||
|
@kernel
|
||||||
|
def run(self):
|
||||||
|
self.core.reset()
|
||||||
|
|
||||||
|
self.core.break_realtime()
|
||||||
|
t = now_mu() - self.core.seconds_to_mu(0.2)
|
||||||
|
while self.core.get_rtio_counter_mu() < t:
|
||||||
|
pass
|
||||||
|
|
||||||
|
for dac_config_name, dac_config_dev in self.dacs_config:
|
||||||
|
self.set_dac_config(dac_config_dev)
|
||||||
|
|
||||||
|
for dac_volt_name, dac_volt_dev in self.dac_volt:
|
||||||
|
self.set_test_dac_volt(dac_volt_dev)
|
||||||
|
|
||||||
|
for dac_dds_name, dac_dds_dev in self.dac_dds:
|
||||||
|
self.set_test_dac_dds(dac_dds_dev)
|
||||||
|
|
||||||
|
for dac_trigger_name, dac_trigger_dev in self.dac_trigger:
|
||||||
|
self.set_dac_trigger(dac_trigger_dev)
|
||||||
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20
template.tex
20
template.tex
@ -1,4 +1,4 @@
|
|||||||
\input{preamble.tex}
|
\include{preamble.tex}
|
||||||
\graphicspath{{images}}
|
\graphicspath{{images}}
|
||||||
|
|
||||||
\title{BOARD NAME}
|
\title{BOARD NAME}
|
||||||
@ -12,15 +12,15 @@
|
|||||||
|
|
||||||
\section{Features}
|
\section{Features}
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\item{features}
|
\item{features}
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\section{Applications}
|
\section{Applications}
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\item{applications}
|
\item{applications}
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\section{General Description}
|
\section{General Description}
|
||||||
|
|
||||||
@ -52,8 +52,12 @@
|
|||||||
|
|
||||||
\section{Specifications}
|
\section{Specifications}
|
||||||
|
|
||||||
|
\newpage
|
||||||
|
|
||||||
|
\section{Example ARTIQ code}
|
||||||
|
\section*{}
|
||||||
|
\vspace*{\fill}
|
||||||
|
|
||||||
\finalfootnote
|
\input{footnote.tex}
|
||||||
|
|
||||||
\end{document}
|
\end{document}
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user