fix typo

2118-2128.tex

@@ -4,7 +4,7 @@
 \title{2118 BNC-TTL / 2128 SMA-TTL}
 \author{M-Labs Limited}
 \date{January 2022}
-\revision{Revision 2}
+\revision{Revision 3}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -36,7 +36,7 @@ Each card provides two banks of four digital channels, for a total of eight digi
 
     Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely. Both cards are capable of a minimum pulse width of 3ns.
 
-Note that isolated TTL cards are less suited to low-noise applications as the isolator itself injects noise between primary and secondary sides. Cable shields may also radiate EMI from the isolated grounds. For low-noise applications, use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
+    Isolated TTL cards are not well suited to low-noise or low-jitter applications due to interference from isolation components. For low-noise applications, use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
 
 % Switch to next column
 \vfill\break
@@ -295,11 +295,11 @@ Note that isolated TTL cards are less suited to low-noise applications as the is
 \begin{figure}[hbt!]
     \centering
     \includegraphics[height=1.8in]{photo2118-2128.jpg }
-    \caption{BNC-TTL and SMA-TTL cards}%
+    \caption{BNC-TTL and SMA-TTL cards}
-    \includegraphics[angle=90, height=0.7in]{DIO_BNC_FP.jpg}
+    \includegraphics[angle=90, height=0.7in]{fp2118.jpg}
-    \includegraphics[angle=90, height=0.4in]{DIO_SMA_FP.jpg}
+    \includegraphics[angle=90, height=0.4in]{fp2128.jpg}
-    \caption{BNC-TTL and SMA-TTL front panels}%
+    \caption{BNC-TTL and SMA-TTL front panels}
-    \label{fig:example}%
+    \label{fig:example}
 \end{figure}
 
 \onecolumn
@@ -359,6 +359,8 @@ Specifications were derived based on the datasheets of the bus transceiver IC (S
     \end{threeparttable}
     \end{table}
 
+    Low-jitter applications should note carefully the jitter introduced by the signal isolator. Noise is also introduced between the primary and secondary domains by the DC/DC converter. Where noise or jitter are crucial, it is instead recommended to use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
+
     Minimum pulse width was measured by generating pulses of progressively longer duration through a DDS generator and using them as input for a BNC-TTL card. The input BNC-TTL card was connected to another BNC-TTL card as output. The output signal is measured and shown in Figure \ref{fig:pulsewidth}.
 
     \begin{figure}[ht]
@@ -395,7 +397,25 @@ IO direction and termination must be configured by setting physical switches on
         \caption{Position of switches}%
     \end{figure}
 
-\newpage
+\sysdescsection
+
+    2118 BNC-TTL and 2128 SMA-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            "name" : {
+                "type": "dio",
+                "board": "DIO_BNC", // or "DIO_SMA", optional
+                "ports": [0],
+                "edge_counter": true, // optional
+                "bank_direction_low": "input", // or "output"
+                "bank_direction_high": "output" // or "input"
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 with the EEM port number used on the core device. Any port can be used. The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false.
+
 \codesection{2118 BNC-TTL/2128 SMA-TTL cards}
 
     Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
@@ -404,21 +424,25 @@ Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTI
     The channel should be configured as output in both the gateware and hardware.
     \inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
 
+\newpage
+
     \subsection{Morse code}
     This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
     \inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
 
-\newpage
     \subsection{Sub-coarse-RTIO-cycle pulse}
     With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
 
     \inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
 
+\newpage
+
     \subsection{Edge counting in a 1ms window}
     The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
     The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
     \inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
     Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
+
     \inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
     The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
     Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
@@ -427,6 +451,7 @@ Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
     The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
 
 \newpage
+
     \subsection{Edge counting using \texttt{EdgeCounter}}
     This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
     \inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
@@ -444,6 +469,7 @@ Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel ca
     \inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
 
 \newpage
+
     \subsection{Minimum sustained event separation}
     The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
 

2238.tex

@@ -4,7 +4,7 @@
 \title{2238 MCX-TTL}
 \author{M-Labs Limited}
 \date{January 2022}
-\revision{Revision 2}
+\revision{Revision 3}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -439,7 +439,7 @@ Each channel supports 50\textOmega~terminations individually controllable using
     \centering
     \includegraphics[height=2in]{photo2238.jpg}
     \caption{MCX-TTL card}
-    \includegraphics[angle=90, height=0.6in]{DIO_MCX_FP.pdf}
+    \includegraphics[angle=90, height=0.6in]{fp2238.pdf}
     \caption{MCX-TTL front panel}
 \end{figure}
 
@@ -505,8 +505,11 @@ All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherw
 \newpage
 
 \section{Configuring IO Direction \& Termination}
+
     IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
+
     \begin{multicols}{2}
+
     Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
 
     \begin{itemize}
@@ -516,15 +519,49 @@ Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note th
         \item IO direction switch open (OFF) \\
             The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
     \end{itemize}
+
     \columnbreak
+
     \begin{center}
         \centering
         \includegraphics[height=1.7in]{mcx_ttl_switches.jpg}
         \captionof{figure}{Position of switches}
     \end{center}
+
     \end{multicols}
 
+\sysdescsection
+
+    2238 MCX-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "dio",
+                "board": "DIO_MCX", // optional
+                "ports": [0],
+                "edge_counter": true, // optional
+                "bank_direction_low": "input", // or "output"
+                "bank_direction_high": "output" // or "input"
+            },
+            {
+                "type": "dio",
+                "board": "DIO_MCX",
+                "ports": [1],
+                "bank_direction_low": "output",
+                "bank_direction_high": "output"
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Note that due to its high channel account and double EEM connections 2238 MCX-TTL is entered into a system description as two peripheral entries, each representing two banks.
+
+    The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. Both \texttt{edge\_counter} and IO direction can be specified separately for each entry.
+
+    For single-EEM operation, use only one of two peripheral entries.
+
 \newpage
+
 \codesection{2238 MCX-TTL card}
 
     Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
@@ -538,6 +575,7 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
     \inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
 
 \newpage
+
     \subsection{Edge counting in an 1ms window}
     The channel should be configured as input in both gateware and hardware.
     \inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}

2245.tex

@@ -7,7 +7,7 @@
 \title{2245 LVDS-TTL}
 \author{M-Labs Limited}
 \date{January 2022}
-\revision{Revision 2}
+\revision{Revision 3}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -297,7 +297,7 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
 \begin{figure}[hbt!]
     \centering
     \includegraphics[angle=90, height=1.7in]{photo2245.jpg}
-    \includegraphics[angle=90, height=0.4in]{DIO_RJ45_FP.pdf}
+    \includegraphics[angle=90, height=0.4in]{fp2245.pdf}
     \caption{LVDS-TTL card and front panel}
 \end{figure}
 
@@ -312,7 +312,7 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
 
     All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
 
-\begin{table}[h]
+    \begin{table}[h!]
     \begin{threeparttable}
     \caption{Recommended Input Voltage}
     \begin{tabularx}{\textwidth}{l | c | c c c | c | X}
@@ -334,7 +334,7 @@ All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherw
 
     All typical values of DC specifications are at $T_A = 25\degree C$.
 
-\begin{table}[h]
+    \begin{table}[h!]
     \begin{threeparttable}
     \caption{DC Specifications}
     \begin{tabularx}{\textwidth}{l | c | c c c | c | X}
@@ -360,7 +360,7 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
 
     All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
 
-\begin{table}[h]
+    \begin{table}[h!]
     \begin{threeparttable}
     \caption{AC Specifications}
     \begin{tabularx}{\textwidth}{l | c c c | c | X}
@@ -379,6 +379,20 @@ All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 30
         LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
         deterministic & & & & & 800 Mbps\\
         \hline
+    \end{tabularx}
+    \end{threeparttable}
+    \end{table}
+
+\newpage
+
+    \begin{table}[h!]
+        \begin{threeparttable}
+        \caption{AC Specifications, cont.}
+        \begin{tabularx}{\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \hline
             LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
             random (RMS) & & & & & \\
             \thickhline
@@ -386,10 +400,10 @@ All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 30
         \end{threeparttable}
         \end{table}
 
-\newpage
-
 \section{Configuring IO Direction \& Termination}
+
     \begin{multicols}{2}
+
     The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
     \begin{itemize}
         \itemsep0em
@@ -400,13 +414,45 @@ The IO direction of each channel can be configured by DIP switches, which are fo
     \end{itemize}
 
     \vspace*{\fill}\columnbreak
+
     \begin{center}
         \centering
         \includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
         \captionof{figure}{Position of switches}
     \end{center}
+
     \end{multicols}
 
+\sysdescsection
+
+    2245 LVDS-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "dio",
+                "board": "DIO_LVDS", // optional
+                "ports": [0],
+                "edge_counter": true, // optional
+                "bank_direction_low": "input", // or "output"
+                "bank_direction_high": "output" // or "input"
+            },
+            {
+                "type": "dio",
+                "board": "DIO_LVDS",
+                "ports": [1],
+                "bank_direction_low": "output",
+                "bank_direction_high": "output"
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Note that due to its high channel account and double EEM connections 2245 LVDS-TTL is entered into a system description as two peripheral entries, each representing two banks.
+
+    The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. Both \texttt{edge\_counter} and IO direction can be specified separately for each entry.
+
+    For single-EEM operation, use only one of two peripheral entries.
+
 \newpage
 
 \codesection{2245 LVDS-TTL card}
@@ -422,6 +468,7 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
     \inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
 
 \newpage
+
     \subsection{Counting rising edges in a 1ms window}
     The channel should be configured as input in both gateware and hardware.
     \inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
@@ -447,7 +494,6 @@ One channel needs to be configured as input, and the other as output.
     \noindent\strut\usebox0\par
     \egroup}
 
-\newpage
     \subsection{SPI Master Device}
     If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
     \begin{enumerate}
@@ -482,8 +528,10 @@ The list of configurations supported in the gateware are listed as below:
         \end{tabular}
     \end{table}
 
-The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves.
+    The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves. The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
-The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
+
+\newpage
+
     \begin{center}
         \begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
             % SPI master
@@ -551,7 +599,6 @@ The direction switches on the LVDS-TTL card should be set to the correct IO dire
         \end{circuitikz}
     \end{center}
 
-\newpage
     \subsubsection{SPI Configuration}
     The following examples will assume the SPI communication has the following properties:
     \begin{itemize}
@@ -561,6 +608,9 @@ The following examples will assume the SPI communication has the following prope
         \item Most significant bit (MSB) first
         \item Full duplex
     \end{itemize}
+
+\newpage
+
     The baseline configuration for an \texttt{SPIMaster} instance can be defined as such:
     \inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
     The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
@@ -590,10 +640,11 @@ Typically, an SPI write operation involves sending an instruction and data to th
     \end{tikztimingtable}%
     \end{center}
 
-\newpage
     Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
     \inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
 
+\newpage
+
     \subsubsection{SPI read}
     A 32-bit read is represented by the following timing diagram:
 
@@ -619,7 +670,6 @@ A 32-bit read is represented by the following timing diagram:
     Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code.
     \inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
 
-\newpage
 \ordersection{2245 LVDS-TTL}
 
 \finalfootnote

4456.tex

@@ -1,10 +1,10 @@
 \input{preamble.tex}
-\graphicspath{{images/4456-4457}{images}}
+\graphicspath{{images/4456}{images}}
 
-\title{4456 Synthesizer Mirny / 4457 HF Synthesizer Mirny + Almazny}
+\title{4456 Synthesizer Mirny}
 \author{M-Labs Limited}
-\date{January 2025}
+\date{January 2022}
-\revision{Revision 2}
+\revision{Revision 1}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -13,11 +13,12 @@
 \section{Features}
 
 \begin{itemize}
-    \item{4-channel wide-band PLL/VCO-based microwave frequency synthesiser}
+\item{4-channel VCO/PLL}
-    \item{Output frequency ranges from 53 MHz to \textgreater 4 GHz for 4456 Mirny only}
+\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz}
-    \item{Up to 12 GHz with 4457 Almazny}
+\item{Up to 13.6 GHz with Almazny mezzanine}
-    \item{Higher frequency resolution than 4410/4412 Urukul}
+\item{Higher frequency resolution than Urukul}
-    \item{Lower jitter, phase noise than 4410/4412 Urukul}
+\item{Lower jitter and phase noise}
+\item{Large frequency changes take several milliseconds}
 \end{itemize}
 
 \section{Applications}
@@ -29,11 +30,12 @@
 \end{itemize}
 
 \section{General Description}
-    The 4456 Synthesizer Mirny card is a 4hp EEM module; the 4457 HF Synthesizer Mirny + Almazny card, consisting of 4456 Mirny plus the 4-channel Almazny HF mezzanine, is a 8hp EEM module. Both Synthesizer cards add microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+The 4456 Synthesizer Mirny card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
 
-    Both cards provide 4 channels of PLL frequency synthesis. 4456 Synthesizer Mirny supports output frequencies from 53 MHz to \textgreater 4GHz. As 4457 HF Synthesizer with Almazny mezzanine this range is expanded up to 12 GHz.
+It provides 4 channels of PLL frequency synthesis. Output frequencies from 53 MHz to \textgreater 4 GHz are supported.The range can be expanded up to 13.6 GHz with the Almazny mezzanine (4467 HF Synthesizer).
+
+Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provides at least 50 dB isolation.
 
-    Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provide at least 50 dB isolation.
 
 % Switch to next column
 \vfill\break
@@ -273,35 +275,21 @@
 
 \begin{figure}[hbt!]
     \centering
-    \includegraphics[height=2in]{photo4457.jpg}
+    \includegraphics[height=2in]{photo4456.jpg}
-    \caption{Mirny + Almazny card}
+    \includegraphics[height=3in, angle=90]{Mirny_FP.pdf}
+    \caption{Mirny card and front panel}
 \end{figure}
 
 % For wide tables, a single column layout is better. It can be switched
 % page-by-page.
 \onecolumn
 
-\begin{figure}[hbt!]
+\sourcesection{4456 Synthesizer Mirny}{https://github.com/sinara-hw/mirny}
-    \subfloat[\centering Mirny and Almazny front panels]{{
-        \begin{minipage}[b]{0.5\linewidth}
-            \centering
-            \includegraphics[height=3in, angle=90]{fp4456.pdf} \\
-            \vspace{0.2in}
-            \includegraphics[height=3in, angle=90]{fp4457.pdf}
-            \vspace{0.25in}
-        \end{minipage}
-    }}
-    \subfloat[\centering Mirny, top-down view]{{
-        \includegraphics[height=2.5in]{photo4456.jpg}
-    }}
-\end{figure}
-
-\sourcesectiond{4456 Synthesizer Mirny}{the 4457 Almazny mezzanine}{https://github.com/sinara-hw/mirny}{https://github.com/sinara-hw/Almazny}
 
 \section{Electrical Specifications}
 
 Specifications of parameters are based on the datasheets of the PLL IC
-    (ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}} for 4456 Mirny, ADF5355\footnote{\label{adf5355}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5355.pdf}}) for 4457 Almazny),
+(ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}}),
 clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}}),
 and digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}).
 Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}\url{https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}}.
@@ -338,41 +326,28 @@
     \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
     \textbf{Unit} & \textbf{Conditions} \\
     \hline
-        Frequency & 53.125 &  & 4000 & MHz & 4456 Mirny only \\
+    Frequency & 53.125 &  & 4000 & MHz & \\
-        & & & 12000 & MHz & With Almazny mezzanine \\
     \hline
     Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
     \hline
+    Resolution & \multicolumn{4}{c|}{} & \\
+    \hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{4}{c|}{52 bits} & \\
+    \hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{4}{c|}{24 bits} & \\
+    \hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{4}{c|}{0.5 dB} & \\
+    \thickhline
 \end{tabularx}
 \end{threeparttable}
 \end{table}
 
 \newpage
 
-\begin{table}[h]
+Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
-    \centering
-    \begin{threeparttable}
-    \caption{Output Specifications, cont.}
-    \begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
-        \thickhline
-        \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
-        \textbf{Unit} & \textbf{Conditions} \\
-        \hline
-        Lock time & & 1.7 & & ms & 4456 Mirny channels \\
-        & & 3.5 & & ms & 4457 Almazny channels \\
-        \hline
-        Resolution & & & & \\
-        \hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{3}{c|}{52} & bits & \\
-        \hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{3}{c|}{24} & bits & \\
-        \hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{3}{c|}{0.5} & dB & \\
-        \thickhline
-    \end{tabularx}
-    \end{threeparttable}
-    \end{table}
-
-    Phase noise performance of 4456 Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. 4456 Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
 
 Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
+\begin{itemize}
+    \item Red: Before any modifications
+    \item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
+\end{itemize}
 
 \begin{figure}[H]
     \centering
@@ -380,13 +355,6 @@
     \caption{Phase noise measurement at 1 GHz}
 \end{figure}
 
-    \begin{itemize}
-        \item Red: Before any modifications
-        \item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
-    \end{itemize}
-
-\newpage
-
 Phase noise at different output frequencies is then measured:
 
 \newcolumntype{Y}{>{\centering\arraybackslash}X}
@@ -415,59 +383,21 @@
 \end{threeparttable}
 \end{table}
 
+\newpage
+
 \begin{figure}[H]
     \centering
     \includegraphics[height=3in]{mirny_phase_noise_frequency.png}
     \caption{Phase noise measurement}
 \end{figure}
 
-\section{Programmable LEDs}
+\codesection{4456 Synthesizer Mirny}
-
-    4456 Mirny features several status LEDs, including a two per output channel. One per channel displays RF switch status.
-
-    The 4457 Almazny mezzanine features an additional row of LEDs, one per output channel, without a fixed purpose. The associated ARTIQ module allows programming these directly through the channel \texttt{set} method.
-
-\newpage
-\sysdescsection
-
-    4456 Synthesizer Mirny must be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
-
-    \begin{tcolorbox}[colback=white]
-        \begin{minted}{json}
-            {
-                "type": "mirny",
-                "ports": 0,
-                "clk_sel": "mmcx", // optional
-                "refclk": 125e6 // optional
-            }
-        \end{minted}
-    \end{tcolorbox}
-
-    Replace 0 with the EEM port number used on the core device. Any port can be used. The \texttt{clk\_sel} field is optional and may be specified as one of either \texttt{xo}, \texttt{mmcx}, or \texttt{sma}. The default is \texttt{xo}. The \texttt{refclk} field is optional and the default is \texttt{100e6}.
-
-    For 4457 Mirny + Almazny, one field must be added:
-
-    \begin{tcolorbox}[colback=white]
-        \begin{minted}{json}
-            {
-                "type": "mirny",
-                "almazny": true,
-                "ports": 0
-            }
-        \end{minted}
-    \end{tcolorbox}
-
-\codesection{4456 Synthesizer Mirny and 4457 Mirny + Almazny}
 
 \subsection{1 GHz sinusoidal wave}
 Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.
 
 \inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
 
-    \subsection{Almazny paired output}
-
-    Mirny and Almazny output channels are paired, and Almazny output channels output twice the frequency of the main Mirny outputs. To set Almazny HF outputs for 4457 HF Synthesizer, set the Mirny outputs to one-half the desired frequency. The above code, run with 4457 HF Synthesizer, will also output 2GHz from Almazny HF0.
-
 \subsection{ADF5356 power control}
 Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:
 
@@ -496,7 +426,7 @@
 
 \inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
 
-\ordersection{4456 Synthesizer Mirny or 4457 HF Synthesizer Mirny + Almazny}
+\ordersection{4456 Synthesizer Mirny}
 
 \finalfootnote
 

examples/unsorted

@@ -0,0 +1,99 @@
+from artiq.experiment import *
+
+class SineWave(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+
+        self.leds = dict()
+        self.ttl_outs = dict()
+        
+        self.dacs_config = dict()
+        self.dac_volt = dict()
+        self.dac_dds = dict()
+        self.dac_trigger = dict()
+        
+        ddb = self.get_device_db()
+        for name, desc in ddb.items():
+            if isinstance(desc, dict) and desc["type"] == "local":
+                module, cls = desc["module"], desc["class"]
+                if (module, cls) == ("artiq.coredevice.ttl", "TTLOut"):
+                    dev = self.get_device(name)
+                    if "led" in name: 
+                        self.leds[name] = dev
+                    else:
+                        self.ttl_outs[name] = dev
+                
+                if (module, cls) == ("artiq.coredevice.shuttler", "Config"):
+                    dev = self.get_device(name)
+                    self.dacs_config[name] = dev
+
+                if (module, cls) == ("artiq.coredevice.shuttler", "Volt"):
+                    dev = self.get_device(name)
+                    self.dac_volt[name] = dev
+                
+                if (module, cls) == ("artiq.coredevice.shuttler", "Dds"):
+                    dev = self.get_device(name)
+                    self.dac_dds[name] = dev
+                
+                if (module, cls) == ("artiq.coredevice.shuttler", "Trigger"):
+                    dev = self.get_device(name)
+                    self.dac_trigger[name] = dev
+                
+        
+        self.leds = sorted(self.leds.items(), key=lambda x: x[1].channel)
+        self.ttl_outs = sorted(self.ttl_outs.items(), key=lambda x: x[1].channel)
+
+        self.dacs_config = sorted(self.dacs_config.items(), key=lambda x: x[1].channel)
+        self.dac_volt = sorted(self.dac_volt.items(), key=lambda x: x[1].channel)
+        self.dac_dds = sorted(self.dac_dds.items(), key=lambda x: x[1].channel)
+        self.dac_trigger = sorted(self.dac_trigger.items(), key=lambda x: x[1].channel)
+        
+
+    @kernel
+    def set_dac_config(self, config):
+        config.set_config(0xFFFF)
+
+    @kernel
+    def set_test_dac_volt(self, volt):
+        a0 = 0
+        a1 = 0
+        a2 = 0
+        a3 = 0
+        volt.set_waveform(a0, a1, a2, a3)
+
+
+    @kernel
+    def set_test_dac_dds(self, dds):
+        b0 = 0x0FFF 
+        b1 = 0
+        b2 = 0
+        b3 = 0
+        c0 = 0
+        c1 = 0x147AE148 # Frequency = 10MHz
+        c2 = 0
+        dds.set_waveform(b0, b1, b2, b3, c0, c1, c2)
+    
+    @kernel
+    def set_dac_trigger(self, trigger):
+        trigger.trigger(0xFFFF)
+
+    @kernel
+    def run(self):
+        self.core.reset()
+
+        self.core.break_realtime()
+        t = now_mu() - self.core.seconds_to_mu(0.2)
+        while self.core.get_rtio_counter_mu() < t:
+            pass
+
+        for dac_config_name, dac_config_dev in self.dacs_config:
+            self.set_dac_config(dac_config_dev)
+
+        for dac_volt_name, dac_volt_dev in self.dac_volt:
+            self.set_test_dac_volt(dac_volt_dev)
+
+        for dac_dds_name, dac_dds_dev in self.dac_dds:
+            self.set_test_dac_dds(dac_dds_dev) 
+
+        for dac_trigger_name, dac_trigger_dev in self.dac_trigger:
+             self.set_dac_trigger(dac_trigger_dev)