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2118-2128.tex
308
2118-2128.tex
@ -4,7 +4,7 @@
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\title{2118 BNC-TTL / 2128 SMA-TTL}
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\author{M-Labs Limited}
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\date{January 2022}
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\revision{Revision 2}
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\revision{Revision 3}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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@ -13,30 +13,30 @@
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\section{Features}
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\begin{itemize}
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\item{8 TTL channels}
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\item{Input- and output-capable}
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\item{Galvanically isolated}
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\item{3ns minimum pulse width}
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\item{BNC or SMA connectors}
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\item{8 TTL channels}
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\item{Input- and output-capable}
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\item{Galvanically isolated}
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\item{3ns minimum pulse width}
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\item{BNC or SMA connectors}
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\end{itemize}
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\section{Applications}
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\begin{itemize}
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\item{Photon counting}
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\item{External equipment trigger}
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\item{Optical shutter control}
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\item{Photon counting}
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\item{External equipment trigger}
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\item{Optical shutter control}
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\end{itemize}
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\section{General Description}
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The 2118 BNC-TTL card is an 8hp EEM module; the 2128 SMA-TTL is a 4hp EEM module. Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
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The 2118 BNC-TTL card is an 8hp EEM module; the 2128 SMA-TTL is a 4hp EEM module. Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
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Each card provides two banks of four digital channels, for a total of eight digital channels, with respectively either BNC (2118) or SMA (2128) connectors. Each bank possesses individual ground isolation. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
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Each card provides two banks of four digital channels, for a total of eight digital channels, with respectively either BNC (2118) or SMA (2128) connectors. Each bank possesses individual ground isolation. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
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Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely. Both cards are capable of a minimum pulse width of 3ns.
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Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely. Both cards are capable of a minimum pulse width of 3ns.
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Note that isolated TTL cards are less suited to low-noise applications as the isolator itself injects noise between primary and secondary sides. Cable shields may also radiate EMI from the isolated grounds. For low-noise applications, use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
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Isolated TTL cards are not well suited to low-noise or low-jitter applications due to interference from isolation components. For low-noise applications, use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
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% Switch to next column
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\vfill\break
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@ -295,11 +295,11 @@ Note that isolated TTL cards are less suited to low-noise applications as the is
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\begin{figure}[hbt!]
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\centering
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\includegraphics[height=1.8in]{photo2118-2128.jpg }
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\caption{BNC-TTL and SMA-TTL cards}%
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\includegraphics[angle=90, height=0.7in]{DIO_BNC_FP.jpg}
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\includegraphics[angle=90, height=0.4in]{DIO_SMA_FP.jpg}
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\caption{BNC-TTL and SMA-TTL front panels}%
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\label{fig:example}%
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\caption{BNC-TTL and SMA-TTL cards}
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\includegraphics[angle=90, height=0.7in]{fp2118.jpg}
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\includegraphics[angle=90, height=0.4in]{fp2128.jpg}
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\caption{BNC-TTL and SMA-TTL front panels}
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\label{fig:example}
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\end{figure}
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\onecolumn
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@ -307,159 +307,185 @@ Note that isolated TTL cards are less suited to low-noise applications as the is
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\sourcesectiond{2118 BNC-TTL}{2128 SMA-TTL}{https://github.com/sinara-hw/DIO_BNC}{https://github.com/sinara-hw/DIO_SMA}
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\section{Electrical Specifications}
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All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
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Specifications were derived based on the datasheets of the bus transceiver IC (SN74BCT25245DW\footnote{\label{transceiver}\url{https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf}}) and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}}). The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}\url{https://github.com/sinara-hw/sinara/issues/187}}.
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All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
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Specifications were derived based on the datasheets of the bus transceiver IC (SN74BCT25245DW\footnote{\label{transceiver}\url{https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf}}) and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}}). The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}\url{https://github.com/sinara-hw/sinara/issues/187}}.
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\begin{table}[h]
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\begin{threeparttable}
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\caption{Recommended Operating Conditions}
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\begin{tabularx}{\textwidth}{l | c c c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
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\textbf{Unit} & \textbf{Conditions} \\
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\hline
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High-level input voltage\repeatfootnote{transceiver} & 2 & & 5.5* & V & \\
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\hline
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Low-level input voltage\repeatfootnote{transceiver} & -0.5 & & 0.8 & V & \\
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\hline
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Input clamp current\repeatfootnote{transceiver} & & & -18 & mA & termination disabled \\
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\hline
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High-level output current\repeatfootnote{transceiver} & & & -160 & mA & \\
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\hline
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Low-level output current\repeatfootnote{transceiver} & & & 376 & mA & \\
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\thickhline
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\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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\begin{table}[h]
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\begin{threeparttable}
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\caption{Recommended Operating Conditions}
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\begin{tabularx}{\textwidth}{l | c c c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
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\textbf{Unit} & \textbf{Conditions} \\
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\hline
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High-level input voltage\repeatfootnote{transceiver} & 2 & & 5.5* & V & \\
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\hline
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Low-level input voltage\repeatfootnote{transceiver} & -0.5 & & 0.8 & V & \\
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\hline
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Input clamp current\repeatfootnote{transceiver} & & & -18 & mA & termination disabled \\
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\hline
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High-level output current\repeatfootnote{transceiver} & & & -160 & mA & \\
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\hline
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Low-level output current\repeatfootnote{transceiver} & & & 376 & mA & \\
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\thickhline
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\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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\begin{table}[h]
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\begin{threeparttable}
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\caption{Electrical Characteristics}
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\begin{tabularx}{\textwidth}{l | c c c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
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\textbf{Unit} & \textbf{Conditions} \\
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\hline
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High-level output voltage\repeatfootnote{transceiver} & 2 & & & V & $I_{OH}$=-160mA \\
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& 2.7 & & & V & $I_{OH}$=-6mA \\
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\hline
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Low-level output voltage\repeatfootnote{transceiver} & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
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& & & 0.7 & V & $I_{OL}$=376mA \\
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\hline
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Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & 3 & 5 & ns & \\
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\hline
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Pulse width distortion\repeatfootnote{isolator} & & 0.2 & 4.5 & ns & \\
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\hline
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Peak jitter\repeatfootnote{isolator} & & 350 & & ps & \\
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\hline
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Data rate\repeatfootnote{isolator} & 0 & & 150 & Mbps & \\
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\thickhline
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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\begin{table}[h]
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\begin{threeparttable}
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\caption{Electrical Characteristics}
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\begin{tabularx}{\textwidth}{l | c c c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
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\textbf{Unit} & \textbf{Conditions} \\
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\hline
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High-level output voltage\repeatfootnote{transceiver} & 2 & & & V & $I_{OH}$=-160mA \\
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& 2.7 & & & V & $I_{OH}$=-6mA \\
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\hline
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Low-level output voltage\repeatfootnote{transceiver} & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
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& & & 0.7 & V & $I_{OL}$=376mA \\
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\hline
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Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & 3 & 5 & ns & \\
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\hline
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Pulse width distortion\repeatfootnote{isolator} & & 0.2 & 4.5 & ns & \\
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\hline
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Peak jitter\repeatfootnote{isolator} & & 350 & & ps & \\
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\hline
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Data rate\repeatfootnote{isolator} & 0 & & 150 & Mbps & \\
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\thickhline
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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Minimum pulse width was measured by generating pulses of progressively longer duration through a DDS generator and using them as input for a BNC-TTL card. The input BNC-TTL card was connected to another BNC-TTL card as output. The output signal is measured and shown in Figure \ref{fig:pulsewidth}.
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Low-jitter applications should note carefully the jitter introduced by the signal isolator. Noise is also introduced between the primary and secondary domains by the DC/DC converter. Where noise or jitter are crucial, it is instead recommended to use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
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\begin{figure}[ht]
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\centering
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\includegraphics[height=3in]{bnc_ttl_min_pulse_width.png}
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\caption{Minimum pulse width required for BNC-TTL card}
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\label{fig:pulsewidth}
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\end{figure}
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Minimum pulse width was measured by generating pulses of progressively longer duration through a DDS generator and using them as input for a BNC-TTL card. The input BNC-TTL card was connected to another BNC-TTL card as output. The output signal is measured and shown in Figure \ref{fig:pulsewidth}.
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\begin{figure}[ht]
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\centering
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\includegraphics[height=3in]{bnc_ttl_min_pulse_width.png}
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\caption{Minimum pulse width required for BNC-TTL card}
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\label{fig:pulsewidth}
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\end{figure}
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\newpage
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The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly.
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The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly.
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\section{Configuring IO Direction \& Termination}
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IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank.
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IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank.
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\begin{itemize}
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\itemsep0em
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\item IO direction switch closed (\texttt{ON}) \\
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Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
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\item IO direction switch open (OFF) \\
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The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
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\end{itemize}
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\begin{itemize}
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\itemsep0em
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\item IO direction switch closed (\texttt{ON}) \\
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Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
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\item IO direction switch open (OFF) \\
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The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
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\end{itemize}
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\begin{figure}[hbt!]
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\centering
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\subfloat[\centering BNC-TTL]{{
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\includegraphics[height=1.5in]{bnc_ttl_switches.jpg}
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}}%
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\subfloat[\centering SMA-TTL]{{
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\includegraphics[height=1.5in]{sma_ttl_switches.jpg}
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}}%
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\caption{Position of switches}%
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\end{figure}
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\begin{figure}[hbt!]
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\centering
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\subfloat[\centering BNC-TTL]{{
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\includegraphics[height=1.5in]{bnc_ttl_switches.jpg}
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}}%
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\subfloat[\centering SMA-TTL]{{
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\includegraphics[height=1.5in]{sma_ttl_switches.jpg}
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}}%
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\caption{Position of switches}%
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\end{figure}
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\sysdescsection
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2118 BNC-TTL and 2128 SMA-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
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\begin{tcolorbox}[colback=white]
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\begin{minted}{json}
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"name" : {
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"type": "dio",
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"board": "DIO_BNC", // or "DIO_SMA", optional
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"ports": [0],
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"edge_counter": true, // optional
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"bank_direction_low": "input", // or "output"
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"bank_direction_high": "output" // or "input"
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}
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\end{minted}
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\end{tcolorbox}
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Replace 0 with the EEM port number used on the core device. Any port can be used. The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false.
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\newpage
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\codesection{2118 BNC-TTL/2128 SMA-TTL cards}
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Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
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Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
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\subsection{One pulse per second}
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The channel should be configured as output in both the gateware and hardware.
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\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
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\subsection{Morse code}
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This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
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\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
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\subsection{One pulse per second}
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The channel should be configured as output in both the gateware and hardware.
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\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
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\newpage
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\subsection{Sub-coarse-RTIO-cycle pulse}
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With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
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||||
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||||
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
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\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
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||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
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||||
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||||
\subsection{Edge counting in a 1ms window}
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||||
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
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||||
The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
|
||||
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
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||||
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
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||||
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
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||||
The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
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||||
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
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||||
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
|
||||
\subsection{Sub-coarse-RTIO-cycle pulse}
|
||||
With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
|
||||
|
||||
The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
|
||||
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
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||||
|
||||
\newpage
|
||||
\subsection{Edge counting using \texttt{EdgeCounter}}
|
||||
This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
|
||||
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle. Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
|
||||
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
|
||||
\subsection{Edge counting in a 1ms window}
|
||||
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
|
||||
The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
|
||||
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
|
||||
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
|
||||
|
||||
\subsection{62.5 MHz clock signal generation}
|
||||
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal. Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle. Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2.
|
||||
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
|
||||
The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
|
||||
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
|
||||
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
|
||||
|
||||
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
|
||||
|
||||
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
|
||||
The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
|
||||
|
||||
\newpage
|
||||
\subsection{Minimum sustained event separation}
|
||||
The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
|
||||
|
||||
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
|
||||
\subsection{Edge counting using \texttt{EdgeCounter}}
|
||||
This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
|
||||
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle. Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
|
||||
|
||||
\begin{center}
|
||||
\begin{table}[H]
|
||||
\captionof{table}{Minimum sustained event separation of different carriers}
|
||||
\centering
|
||||
\begin{tabular}{|c|c|c|}
|
||||
\hline
|
||||
Carrier & Kasli v1.1 & Kasli-SoC \\ \hline
|
||||
Duration & 650 ns & 600 ns \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
\end{center}
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
|
||||
|
||||
\subsection{62.5 MHz clock signal generation}
|
||||
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal. Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle. Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2.
|
||||
|
||||
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
|
||||
|
||||
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
|
||||
\subsection{Minimum sustained event separation}
|
||||
The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
|
||||
|
||||
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
|
||||
|
||||
\begin{center}
|
||||
\begin{table}[H]
|
||||
\captionof{table}{Minimum sustained event separation of different carriers}
|
||||
\centering
|
||||
\begin{tabular}{|c|c|c|}
|
||||
\hline
|
||||
Carrier & Kasli v1.1 & Kasli-SoC \\ \hline
|
||||
Duration & 650 ns & 600 ns \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
\end{center}
|
||||
|
||||
\ordersection{2118 BNC-TTL/2128 SMA-TTL}
|
||||
|
||||
|
||||
226
2238.tex
226
2238.tex
@ -4,7 +4,7 @@
|
||||
\title{2238 MCX-TTL}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2022}
|
||||
\revision{Revision 2}
|
||||
\revision{Revision 3}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -13,28 +13,28 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{16 MCX-TTL channels}
|
||||
\item{Input and output capable}
|
||||
\item{No galvanic isolation}
|
||||
\item{High speed and low jitter}
|
||||
\item{MCX connectors}
|
||||
\item{16 MCX-TTL channels}
|
||||
\item{Input and output capable}
|
||||
\item{No galvanic isolation}
|
||||
\item{High speed and low jitter}
|
||||
\item{MCX connectors}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Photon counting}
|
||||
\item{External equipment trigger}
|
||||
\item{Optical shutter control}
|
||||
\item{Photon counting}
|
||||
\item{External equipment trigger}
|
||||
\item{Optical shutter control}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
|
||||
The 2238 MCX-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
The 2238 MCX-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
Each card provides four banks of four digital channels each for a total of sixteen digital channels, with MCX connectors in the front panel, controlled through two EEM connectors. Each individual EEM connector controls two banks independently. Single EEM operation is possible. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
|
||||
Each card provides four banks of four digital channels each for a total of sixteen digital channels, with MCX connectors in the front panel, controlled through two EEM connectors. Each individual EEM connector controls two banks independently. Single EEM operation is possible. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
|
||||
|
||||
Each channel supports 50\textOmega~terminations individually controllable using DIP switches. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
|
||||
Each channel supports 50\textOmega~terminations individually controllable using DIP switches. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
@ -439,7 +439,7 @@ Each channel supports 50\textOmega~terminations individually controllable using
|
||||
\centering
|
||||
\includegraphics[height=2in]{photo2238.jpg}
|
||||
\caption{MCX-TTL card}
|
||||
\includegraphics[angle=90, height=0.6in]{DIO_MCX_FP.pdf}
|
||||
\includegraphics[angle=90, height=0.6in]{fp2238.pdf}
|
||||
\caption{MCX-TTL front panel}
|
||||
\end{figure}
|
||||
|
||||
@ -451,104 +451,142 @@ Each channel supports 50\textOmega~terminations individually controllable using
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the bus transceiver IC (74LVT162245MTD\footnote{\label{transceiver}\url{https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}}).
|
||||
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the bus transceiver IC (74LVT162245MTD\footnote{\label{transceiver}\url{https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}}).
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input voltage & 0 & & 5.5* & V \\
|
||||
\hline
|
||||
High-level output current & & & -24 & mA \\
|
||||
\hline
|
||||
Low-level output current & & & 24 & mA \\
|
||||
\hline
|
||||
Input edge rate & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
|
||||
\thickhline
|
||||
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input voltage & 0 & & 5.5* & V \\
|
||||
\hline
|
||||
High-level output current & & & -24 & mA \\
|
||||
\hline
|
||||
Low-level output current & & & 24 & mA \\
|
||||
\hline
|
||||
Input edge rate & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
|
||||
\thickhline
|
||||
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input clamp diode voltage & & & -1.2 & V & $I_I =-36 mA$ \\
|
||||
\hline
|
||||
Input high voltage & 2.0 & & & V & \\
|
||||
\hline
|
||||
Input low voltage & & & 0.8 & V & \\
|
||||
\hline
|
||||
Output high voltage & 2.0 & & & V & $I_{OH}=-24mA$ \\
|
||||
& 3.1 & & & V & $I_{OH}=-200\mu A$ \\
|
||||
\hline
|
||||
Output low voltage & & & 0.8 & V & $I_{OL}=-24mA$ \\
|
||||
& & & 0.2 & V & $I_{OL}=-200\mu A$ \\
|
||||
\hline
|
||||
Input current & & & 20 & \textmu A & $V_I=5.5V$ \\
|
||||
& & & 2 & \textmu A & $V_I=3.3V$ \\
|
||||
& & & -10 & \textmu A & $V_I=0V$ \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input clamp diode voltage & & & -1.2 & V & $I_I =-36 mA$ \\
|
||||
\hline
|
||||
Input high voltage & 2.0 & & & V & \\
|
||||
\hline
|
||||
Input low voltage & & & 0.8 & V & \\
|
||||
\hline
|
||||
Output high voltage & 2.0 & & & V & $I_{OH}=-24mA$ \\
|
||||
& 3.1 & & & V & $I_{OH}=-200\mu A$ \\
|
||||
\hline
|
||||
Output low voltage & & & 0.8 & V & $I_{OL}=-24mA$ \\
|
||||
& & & 0.2 & V & $I_{OL}=-200\mu A$ \\
|
||||
\hline
|
||||
Input current & & & 20 & \textmu A & $V_I=5.5V$ \\
|
||||
& & & 2 & \textmu A & $V_I=3.3V$ \\
|
||||
& & & -10 & \textmu A & $V_I=0V$ \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
|
||||
\section{Configuring IO Direction \& Termination}
|
||||
IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
|
||||
\begin{multicols}{2}
|
||||
Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
|
||||
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item IO direction switch closed (\texttt{ON}) \\
|
||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item IO direction switch open (OFF) \\
|
||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.7in]{mcx_ttl_switches.jpg}
|
||||
\captionof{figure}{Position of switches}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
|
||||
|
||||
\begin{multicols}{2}
|
||||
|
||||
Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
|
||||
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item IO direction switch closed (\texttt{ON}) \\
|
||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item IO direction switch open (OFF) \\
|
||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.7in]{mcx_ttl_switches.jpg}
|
||||
\captionof{figure}{Position of switches}
|
||||
\end{center}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
\sysdescsection
|
||||
|
||||
2238 MCX-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "dio",
|
||||
"board": "DIO_MCX", // optional
|
||||
"ports": [0],
|
||||
"edge_counter": true, // optional
|
||||
"bank_direction_low": "input", // or "output"
|
||||
"bank_direction_high": "output" // or "input"
|
||||
},
|
||||
{
|
||||
"type": "dio",
|
||||
"board": "DIO_MCX",
|
||||
"ports": [1],
|
||||
"bank_direction_low": "output",
|
||||
"bank_direction_high": "output"
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
Note that due to its high channel account and double EEM connections 2238 MCX-TTL is entered into a system description as two peripheral entries, each representing two banks.
|
||||
|
||||
The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. Both \texttt{edge\_counter} and IO direction can be specified separately for each entry.
|
||||
|
||||
For single-EEM operation, use only one of two peripheral entries.
|
||||
|
||||
\newpage
|
||||
|
||||
\codesection{2238 MCX-TTL card}
|
||||
|
||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
|
||||
\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
\subsection{Edge counting in an 1ms window}
|
||||
The channel should be configured as input in both gateware and hardware.
|
||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||
|
||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
||||
\subsection{Edge counting in an 1ms window}
|
||||
The channel should be configured as input in both gateware and hardware.
|
||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
||||
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||
|
||||
\ordersection{2238 MCX-TTL}
|
||||
|
||||
|
||||
610
2245.tex
610
2245.tex
@ -7,7 +7,7 @@
|
||||
\title{2245 LVDS-TTL}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2022}
|
||||
\revision{Revision 2}
|
||||
\revision{Revision 3}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -16,28 +16,28 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{16 LVDS-TTL channels.}
|
||||
\item{Input- and output-capable}
|
||||
\item{No galvanic isolation}
|
||||
\item{High speed and low jitter}
|
||||
\item{RJ45 connectors}
|
||||
\item{16 LVDS-TTL channels.}
|
||||
\item{Input- and output-capable}
|
||||
\item{No galvanic isolation}
|
||||
\item{High speed and low jitter}
|
||||
\item{RJ45 connectors}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Photon counting}
|
||||
\item{External equipment trigger}
|
||||
\item{Optical shutter control}
|
||||
\item{Serial communication with remote devices}
|
||||
\item{Photon counting}
|
||||
\item{External equipment trigger}
|
||||
\item{Optical shutter control}
|
||||
\item{Serial communication with remote devices}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 2245 LVDS-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
The 2245 LVDS-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
Each card provides sixteen total digital channels, with four RJ45 connectors in the front panel, controlled through 2 EEM connectors. Each RJ45 connector exposes four LVDS digital channels. Each individual EEM connector controls eight channels independently. Single EEM operation is possible. The direction (input or output) of each channel can be selected individually using DIP switches.
|
||||
Each card provides sixteen total digital channels, with four RJ45 connectors in the front panel, controlled through 2 EEM connectors. Each RJ45 connector exposes four LVDS digital channels. Each individual EEM connector controls eight channels independently. Single EEM operation is possible. The direction (input or output) of each channel can be selected individually using DIP switches.
|
||||
|
||||
Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~terminated. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards. Only shielded Ethernet Cat-6 cables should be connected.
|
||||
Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~terminated. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards. Only shielded Ethernet Cat-6 cables should be connected.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
@ -297,7 +297,7 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[angle=90, height=1.7in]{photo2245.jpg}
|
||||
\includegraphics[angle=90, height=0.4in]{DIO_RJ45_FP.pdf}
|
||||
\includegraphics[angle=90, height=0.4in]{fp2245.pdf}
|
||||
\caption{LVDS-TTL card and front panel}
|
||||
\end{figure}
|
||||
|
||||
@ -310,316 +310,366 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
|
||||
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Input Voltage}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Magnitude of differential input & $|V_{ID}|$ & 0.1 & & 3.3 & V \\
|
||||
\hline
|
||||
Common mode input & $V_{IC}$ & $|V_{ID}|/2$ & & $3.3-|V_{ID}|/2$ & V \\
|
||||
\hline
|
||||
Differential input threshold HIGH & $V_{TH}$ & & & 100 & mV & \\
|
||||
\hline
|
||||
Differential input threshold LOW & $V_{TL}$ & -100 & & & mV & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h!]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Input Voltage}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Magnitude of differential input & $|V_{ID}|$ & 0.1 & & 3.3 & V \\
|
||||
\hline
|
||||
Common mode input & $V_{IC}$ & $|V_{ID}|/2$ & & $3.3-|V_{ID}|/2$ & V \\
|
||||
\hline
|
||||
Differential input threshold HIGH & $V_{TH}$ & & & 100 & mV & \\
|
||||
\hline
|
||||
Differential input threshold LOW & $V_{TL}$ & -100 & & & mV & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
All typical values of DC specifications are at $T_A = 25\degree C$.
|
||||
All typical values of DC specifications are at $T_A = 25\degree C$.
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{DC Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Output differential voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
|
||||
\cline{0-5}
|
||||
$|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
|
||||
\cline{0-5}
|
||||
Offset voltage & $V_{OS}$ & 1.125 & 1.23 & 1.375 & V & \\
|
||||
\cline{0-5}
|
||||
$|V_{OS}|$ change (LOW-to-HIGH) & $\Delta V_{OS}$ & & & 25 & mV & \\
|
||||
\hline
|
||||
Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
|
||||
\hline
|
||||
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended input voltage \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h!]
|
||||
\begin{threeparttable}
|
||||
\caption{DC Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Output differential voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
|
||||
\cline{0-5}
|
||||
$|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
|
||||
\cline{0-5}
|
||||
Offset voltage & $V_{OS}$ & 1.125 & 1.23 & 1.375 & V & \\
|
||||
\cline{0-5}
|
||||
$|V_{OS}|$ change (LOW-to-HIGH) & $\Delta V_{OS}$ & & & 25 & mV & \\
|
||||
\hline
|
||||
Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
|
||||
\hline
|
||||
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended input voltage \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
|
||||
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{AC Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Differential output rise time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & Duty cycle = 50\%.\\
|
||||
(20\% to 80\%) & & & & & \\
|
||||
\cline{0-5}
|
||||
Differential output fall time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
|
||||
(80\% to 20\%) & & & & & \\
|
||||
\cline{0-5}
|
||||
Pulse width distortion & & 0.01 & 0.2 & ns & \\
|
||||
\hline
|
||||
LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
|
||||
deterministic & & & & & 800 Mbps\\
|
||||
\hline
|
||||
LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
|
||||
random (RMS) & & & & & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h!]
|
||||
\begin{threeparttable}
|
||||
\caption{AC Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Differential output rise time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & Duty cycle = 50\%.\\
|
||||
(20\% to 80\%) & & & & & \\
|
||||
\cline{0-5}
|
||||
Differential output fall time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
|
||||
(80\% to 20\%) & & & & & \\
|
||||
\cline{0-5}
|
||||
Pulse width distortion & & 0.01 & 0.2 & ns & \\
|
||||
\hline
|
||||
LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
|
||||
deterministic & & & & & 800 Mbps\\
|
||||
\hline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
|
||||
\section{Configuring IO Direction \& Termination}
|
||||
\begin{multicols}{2}
|
||||
The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item IO direction switch closed (\texttt{ON}) \\
|
||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item IO direction switch open (OFF) \\
|
||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
\begin{table}[h!]
|
||||
\begin{threeparttable}
|
||||
\caption{AC Specifications, cont.}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
|
||||
random (RMS) & & & & & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\vspace*{\fill}\columnbreak
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
|
||||
\captionof{figure}{Position of switches}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
\section{Configuring IO Direction \& Termination}
|
||||
|
||||
\begin{multicols}{2}
|
||||
|
||||
The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item IO direction switch closed (\texttt{ON}) \\
|
||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item IO direction switch open (OFF) \\
|
||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
|
||||
\vspace*{\fill}\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
|
||||
\captionof{figure}{Position of switches}
|
||||
\end{center}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
\sysdescsection
|
||||
|
||||
2245 LVDS-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "dio",
|
||||
"board": "DIO_LVDS", // optional
|
||||
"ports": [0],
|
||||
"edge_counter": true, // optional
|
||||
"bank_direction_low": "input", // or "output"
|
||||
"bank_direction_high": "output" // or "input"
|
||||
},
|
||||
{
|
||||
"type": "dio",
|
||||
"board": "DIO_LVDS",
|
||||
"ports": [1],
|
||||
"bank_direction_low": "output",
|
||||
"bank_direction_high": "output"
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
Note that due to its high channel account and double EEM connections 2245 LVDS-TTL is entered into a system description as two peripheral entries, each representing two banks.
|
||||
|
||||
The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. Both \texttt{edge\_counter} and IO direction can be specified separately for each entry.
|
||||
|
||||
For single-EEM operation, use only one of two peripheral entries.
|
||||
|
||||
\newpage
|
||||
|
||||
\codesection{2245 LVDS-TTL card}
|
||||
|
||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
|
||||
\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
\subsection{Counting rising edges in a 1ms window}
|
||||
The channel should be configured as input in both gateware and hardware.
|
||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||
|
||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
||||
\subsection{Counting rising edges in a 1ms window}
|
||||
The channel should be configured as input in both gateware and hardware.
|
||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
||||
|
||||
\newcommand{\wrapspacer}[1]% #1 = special text
|
||||
{\bgroup
|
||||
\sbox0{\begin{minipage}{\linewidth}\hrule height0pt
|
||||
#1\hrule height0pt
|
||||
\end{minipage}}%
|
||||
\dimen0=\dimexpr \ht0+\dp0\relax
|
||||
\loop\ifdim\dimen0>\baselineskip
|
||||
\strut\vspace{-\baselineskip}\newline
|
||||
\advance\dimen0 by -\baselineskip
|
||||
\repeat
|
||||
\noindent\strut\usebox0\par
|
||||
\egroup}
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||
|
||||
\newcommand{\wrapspacer}[1]% #1 = special text
|
||||
{\bgroup
|
||||
\sbox0{\begin{minipage}{\linewidth}\hrule height0pt
|
||||
#1\hrule height0pt
|
||||
\end{minipage}}%
|
||||
\dimen0=\dimexpr \ht0+\dp0\relax
|
||||
\loop\ifdim\dimen0>\baselineskip
|
||||
\strut\vspace{-\baselineskip}\newline
|
||||
\advance\dimen0 by -\baselineskip
|
||||
\repeat
|
||||
\noindent\strut\usebox0\par
|
||||
\egroup}
|
||||
|
||||
\subsection{SPI Master Device}
|
||||
If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
|
||||
\begin{enumerate}
|
||||
% The config register can be set using set_config.
|
||||
% However, the only difference between these 2 methods is that set_config accepts an arbitrary
|
||||
% frequency, then translate into the rough frequency divisor for set_config_mu.
|
||||
% It doesn't guarantee such frequency would be set as the SPI frequency
|
||||
|
||||
% In addition, finding clock division is quite easy. set_config_mu seems to be a more
|
||||
% straight-forward & representative of the actual implementation.
|
||||
\item Set the \texttt{config} register (e.g. using \texttt{set\char`_config\char`_mu()}).
|
||||
\item Start the SPI transfer by writing the \texttt{data} register using \texttt{write()}.
|
||||
\item If the data from the SPI slave is to be read (i.e. \texttt{SPI\char`_INPUT} was set in \texttt{config}), invoke \texttt{read()} to read.
|
||||
|
||||
\end{enumerate}
|
||||
|
||||
The list of configurations supported in the gateware are listed as below:
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{tabular}{|c|l|}
|
||||
\hline
|
||||
Flag & Description \\ \hline
|
||||
\texttt{SPI\char`_OFFLINE} & Switch all pins to high impedance mode. \\ \hline
|
||||
\texttt{SPI\char`_END} & Next SPI transfer is the last of the transcation. \\ \hline
|
||||
\texttt{SPI\char`_INPUT} & Submit SPI read data as RTIO input event when the transfer is complete. \\ \hline
|
||||
\texttt{SPI\char`_CS\char`_POLARITY} & Active level of chip select (CS) \\ \hline
|
||||
\texttt{SPI\char`_CLK\char`_POLARITY} & Idle level of serial clock (SCK) \\ \hline
|
||||
\texttt{SPI\char`_CLK\char`_PHASE} & Data is sampled on falling edge \& shifted out on rising edge. \\ \hline
|
||||
\texttt{SPI\char`_LSB\char`_FIRST} & LSB is the first on bit on the wire. \\ \hline
|
||||
\texttt{SPI\char`_HALF\char`_DUPLEX} & Use 3-wire SPI, where MOSI is both input \& output capable. \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves. The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
|
||||
|
||||
\newpage
|
||||
\subsection{SPI Master Device}
|
||||
If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
|
||||
\begin{enumerate}
|
||||
% The config register can be set using set_config.
|
||||
% However, the only difference between these 2 methods is that set_config accepts an arbitrary
|
||||
% frequency, then translate into the rough frequency divisor for set_config_mu.
|
||||
% It doesn't guarantee such frequency would be set as the SPI frequency
|
||||
|
||||
% In addition, finding clock division is quite easy. set_config_mu seems to be a more
|
||||
% straight-forward & representative of the actual implementation.
|
||||
\item Set the \texttt{config} register (e.g. using \texttt{set\char`_config\char`_mu()}).
|
||||
\item Start the SPI transfer by writing the \texttt{data} register using \texttt{write()}.
|
||||
\item If the data from the SPI slave is to be read (i.e. \texttt{SPI\char`_INPUT} was set in \texttt{config}), invoke \texttt{read()} to read.
|
||||
\begin{center}
|
||||
\begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
|
||||
% SPI master
|
||||
\draw (0, 1.8) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=2, scale=1] (master) {};
|
||||
\node [label={center:\large{SPI Master}}] at (-0.6, 2.05) {};
|
||||
\node [label={center:\large{(LVDS-TTL)}}] at (-0.6, 1.55) {};
|
||||
\node [label=left:{SCK}] at (2, 2.8) {};
|
||||
\node [label=left:{MOSI}] at (2, 2.4) {};
|
||||
\node [label=left:{MISO}] at (2, 2.0) {};
|
||||
\node [label=left:{CS0}] at (2, 1.6) {};
|
||||
\node [label=left:{CS1}] at (2, 1.2) {};
|
||||
\node [label=left:{CS2}] at (2, 0.8) {};
|
||||
|
||||
\end{enumerate}
|
||||
% SPI slaves
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, 2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave0) {};
|
||||
\node [label={center:\large{SPI Slave 0}}] at (7.6, 2.2) {};
|
||||
\node [label=right:{SCK}] at (5, 2.8) {};
|
||||
\node [label=right:{MOSI}] at (5, 2.4) {};
|
||||
\node [label=right:{MISO}] at (5, 2.0) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, 1.6) {};
|
||||
|
||||
The list of configurations supported in the gateware are listed as below:
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, 0) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave1) {};
|
||||
\node [label={center:\large{SPI Slave 1}}] at (7.6, 0) {};
|
||||
\node [label=right:{SCK}] at (5, 0.6) {};
|
||||
\node [label=right:{MOSI}] at (5, 0.2) {};
|
||||
\node [label=right:{MISO}] at (5, -0.2) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -0.6) {};
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{tabular}{|c|l|}
|
||||
\hline
|
||||
Flag & Description \\ \hline
|
||||
\texttt{SPI\char`_OFFLINE} & Switch all pins to high impedance mode. \\ \hline
|
||||
\texttt{SPI\char`_END} & Next SPI transfer is the last of the transcation. \\ \hline
|
||||
\texttt{SPI\char`_INPUT} & Submit SPI read data as RTIO input event when the transfer is complete. \\ \hline
|
||||
\texttt{SPI\char`_CS\char`_POLARITY} & Active level of chip select (CS) \\ \hline
|
||||
\texttt{SPI\char`_CLK\char`_POLARITY} & Idle level of serial clock (SCK) \\ \hline
|
||||
\texttt{SPI\char`_CLK\char`_PHASE} & Data is sampled on falling edge \& shifted out on rising edge. \\ \hline
|
||||
\texttt{SPI\char`_LSB\char`_FIRST} & LSB is the first on bit on the wire. \\ \hline
|
||||
\texttt{SPI\char`_HALF\char`_DUPLEX} & Use 3-wire SPI, where MOSI is both input \& output capable. \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, -2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave2) {};
|
||||
\node [label={center:\large{SPI Slave 2}}] at (7.6, -2.2) {};
|
||||
\node [label=right:{SCK}] at (5, -1.6) {};
|
||||
\node [label=right:{MOSI}] at (5, -2.0) {};
|
||||
\node [label=right:{MISO}] at (5, -2.4) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -2.8) {};
|
||||
|
||||
The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves.
|
||||
The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
|
||||
\begin{center}
|
||||
\begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
|
||||
% SPI master
|
||||
\draw (0, 1.8) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=2, scale=1] (master) {};
|
||||
\node [label={center:\large{SPI Master}}] at (-0.6, 2.05) {};
|
||||
\node [label={center:\large{(LVDS-TTL)}}] at (-0.6, 1.55) {};
|
||||
\node [label=left:{SCK}] at (2, 2.8) {};
|
||||
\node [label=left:{MOSI}] at (2, 2.4) {};
|
||||
\node [label=left:{MISO}] at (2, 2.0) {};
|
||||
\node [label=left:{CS0}] at (2, 1.6) {};
|
||||
\node [label=left:{CS1}] at (2, 1.2) {};
|
||||
\node [label=left:{CS2}] at (2, 0.8) {};
|
||||
% Connect the master to slave 0
|
||||
\draw [-latexslim] (1.95, 2.8) -- (5.05, 2.8);
|
||||
\draw [-latexslim] (1.95, 2.4) -- (5.05, 2.4);
|
||||
\draw [latexslim-] (1.95, 2.0) -- (5.05, 2.0);
|
||||
\draw [-latexslim] (1.95, 1.6) -- (5.05, 1.6);
|
||||
|
||||
% SPI slaves
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, 2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave0) {};
|
||||
\node [label={center:\large{SPI Slave 0}}] at (7.6, 2.2) {};
|
||||
\node [label=right:{SCK}] at (5, 2.8) {};
|
||||
\node [label=right:{MOSI}] at (5, 2.4) {};
|
||||
\node [label=right:{MISO}] at (5, 2.0) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, 1.6) {};
|
||||
% Connect slave 1
|
||||
\draw [-latexslim] (4.2, 2.8) -- (4.2, 0.6) -- (5.05, 0.6);
|
||||
\draw [-latexslim] (3.8, 2.4) -- (3.8, 0.2) -- (5.05, 0.2);
|
||||
\draw [-] (3.4, 2.0) -- (3.4, -0.2) -- (5.05, -0.2);
|
||||
\draw [-latexslim] (1.95, 1.2) -- (3.0, 1.2) -- (3.0, -0.6) -- (5.05, -0.6);
|
||||
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, 0) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave1) {};
|
||||
\node [label={center:\large{SPI Slave 1}}] at (7.6, 0) {};
|
||||
\node [label=right:{SCK}] at (5, 0.6) {};
|
||||
\node [label=right:{MOSI}] at (5, 0.2) {};
|
||||
\node [label=right:{MISO}] at (5, -0.2) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -0.6) {};
|
||||
% Connect slave 2
|
||||
\draw [-latexslim] (4.2, 0.6) -- (4.2, -1.6) -- (5.05, -1.6);
|
||||
\draw [-latexslim] (3.8, 0.2) -- (3.8, -2.0) -- (5.05, -2.0);
|
||||
\draw [-] (3.4, -0.2) -- (3.4, -2.4) -- (5.05, -2.4);
|
||||
\draw [-latexslim] (1.95, 0.8) -- (2.6, 0.8) -- (2.6, -2.8) -- (5.05, -2.8);
|
||||
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, -2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave2) {};
|
||||
\node [label={center:\large{SPI Slave 2}}] at (7.6, -2.2) {};
|
||||
\node [label=right:{SCK}] at (5, -1.6) {};
|
||||
\node [label=right:{MOSI}] at (5, -2.0) {};
|
||||
\node [label=right:{MISO}] at (5, -2.4) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -2.8) {};
|
||||
% Add dot to intersection to distinguish from overlaps
|
||||
\node at (4.2, 2.8)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.8, 2.4)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.4, 2.0)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (4.2, 0.6)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.8, 0.2)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.4, -0.2)[circle,fill,inner sep=0.7pt]{};
|
||||
|
||||
% Connect the master to slave 0
|
||||
\draw [-latexslim] (1.95, 2.8) -- (5.05, 2.8);
|
||||
\draw [-latexslim] (1.95, 2.4) -- (5.05, 2.4);
|
||||
\draw [latexslim-] (1.95, 2.0) -- (5.05, 2.0);
|
||||
\draw [-latexslim] (1.95, 1.6) -- (5.05, 1.6);
|
||||
\end{circuitikz}
|
||||
\end{center}
|
||||
|
||||
% Connect slave 1
|
||||
\draw [-latexslim] (4.2, 2.8) -- (4.2, 0.6) -- (5.05, 0.6);
|
||||
\draw [-latexslim] (3.8, 2.4) -- (3.8, 0.2) -- (5.05, 0.2);
|
||||
\draw [-] (3.4, 2.0) -- (3.4, -0.2) -- (5.05, -0.2);
|
||||
\draw [-latexslim] (1.95, 1.2) -- (3.0, 1.2) -- (3.0, -0.6) -- (5.05, -0.6);
|
||||
|
||||
% Connect slave 2
|
||||
\draw [-latexslim] (4.2, 0.6) -- (4.2, -1.6) -- (5.05, -1.6);
|
||||
\draw [-latexslim] (3.8, 0.2) -- (3.8, -2.0) -- (5.05, -2.0);
|
||||
\draw [-] (3.4, -0.2) -- (3.4, -2.4) -- (5.05, -2.4);
|
||||
\draw [-latexslim] (1.95, 0.8) -- (2.6, 0.8) -- (2.6, -2.8) -- (5.05, -2.8);
|
||||
|
||||
% Add dot to intersection to distinguish from overlaps
|
||||
\node at (4.2, 2.8)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.8, 2.4)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.4, 2.0)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (4.2, 0.6)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.8, 0.2)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.4, -0.2)[circle,fill,inner sep=0.7pt]{};
|
||||
|
||||
\end{circuitikz}
|
||||
\end{center}
|
||||
\subsubsection{SPI Configuration}
|
||||
The following examples will assume the SPI communication has the following properties:
|
||||
\begin{itemize}
|
||||
\item Chip select (CS) is active low
|
||||
\item Serial clock (SCK) idle level is low
|
||||
\item Data is sampled on rising edge of SCK \& shifted out on falling edge of SCK
|
||||
\item Most significant bit (MSB) first
|
||||
\item Full duplex
|
||||
\end{itemize}
|
||||
|
||||
\newpage
|
||||
\subsubsection{SPI Configuration}
|
||||
The following examples will assume the SPI communication has the following properties:
|
||||
\begin{itemize}
|
||||
\item Chip select (CS) is active low
|
||||
\item Serial clock (SCK) idle level is low
|
||||
\item Data is sampled on rising edge of SCK \& shifted out on falling edge of SCK
|
||||
\item Most significant bit (MSB) first
|
||||
\item Full duplex
|
||||
\end{itemize}
|
||||
The baseline configuration for an \texttt{SPIMaster} instance can be defined as such:
|
||||
\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
|
||||
The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
|
||||
|
||||
\subsubsection{SPI frequency}
|
||||
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor in [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
|
||||
\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
|
||||
The baseline configuration for an \texttt{SPIMaster} instance can be defined as such:
|
||||
\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
|
||||
The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
|
||||
|
||||
\subsubsection{SPI write}
|
||||
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. Suppose the instruction and data are 8 bits and 32 bits respectively. The timing diagram of such a write operation is shown in the following:
|
||||
\subsubsection{SPI frequency}
|
||||
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor in [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
|
||||
\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
|
||||
|
||||
\begin{center}
|
||||
\begin{tikztimingtable}
|
||||
[
|
||||
timing/d/background/.style={fill=white},
|
||||
timing/lslope=0.2
|
||||
]
|
||||
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
||||
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
||||
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
||||
% then print the label from macro. But it turns out tikz-timing will print
|
||||
% the counter value separately, even with an additional macro.
|
||||
% Therefore, it does not work properly.
|
||||
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}, timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
||||
UJ{7}8{2I}R{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
||||
MOSI & 53U \\
|
||||
\end{tikztimingtable}%
|
||||
\end{center}
|
||||
\subsubsection{SPI write}
|
||||
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. Suppose the instruction and data are 8 bits and 32 bits respectively. The timing diagram of such a write operation is shown in the following:
|
||||
|
||||
\begin{center}
|
||||
\begin{tikztimingtable}
|
||||
[
|
||||
timing/d/background/.style={fill=white},
|
||||
timing/lslope=0.2
|
||||
]
|
||||
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
||||
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
||||
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
||||
% then print the label from macro. But it turns out tikz-timing will print
|
||||
% the counter value separately, even with an additional macro.
|
||||
% Therefore, it does not work properly.
|
||||
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}, timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
||||
UJ{7}8{2I}R{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
||||
MOSI & 53U \\
|
||||
\end{tikztimingtable}%
|
||||
\end{center}
|
||||
|
||||
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
|
||||
\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
|
||||
|
||||
\newpage
|
||||
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
|
||||
\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
|
||||
|
||||
\subsubsection{SPI read}
|
||||
A 32-bit read is represented by the following timing diagram:
|
||||
\subsubsection{SPI read}
|
||||
A 32-bit read is represented by the following timing diagram:
|
||||
|
||||
\begin{center}
|
||||
\begin{tikztimingtable}
|
||||
[
|
||||
timing/d/background/.style={fill=white},
|
||||
timing/lslope=0.2
|
||||
]
|
||||
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
||||
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
||||
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
||||
% then print the label from macro. But it turns out tikz-timing will print
|
||||
% the counter value separately, even with an additional macro.
|
||||
% Therefore, it does not work properly.
|
||||
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}]
|
||||
UJ{7}8{2I}36U \\
|
||||
MOSI & [timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
||||
17UR{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
||||
\end{tikztimingtable}%
|
||||
\end{center}
|
||||
\begin{center}
|
||||
\begin{tikztimingtable}
|
||||
[
|
||||
timing/d/background/.style={fill=white},
|
||||
timing/lslope=0.2
|
||||
]
|
||||
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
||||
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
||||
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
||||
% then print the label from macro. But it turns out tikz-timing will print
|
||||
% the counter value separately, even with an additional macro.
|
||||
% Therefore, it does not work properly.
|
||||
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}]
|
||||
UJ{7}8{2I}36U \\
|
||||
MOSI & [timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
||||
17UR{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
||||
\end{tikztimingtable}%
|
||||
\end{center}
|
||||
|
||||
Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code.
|
||||
\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
|
||||
Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code.
|
||||
\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
|
||||
|
||||
\newpage
|
||||
\ordersection{2245 LVDS-TTL}
|
||||
|
||||
\finalfootnote
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/4456-4457}{images}}
|
||||
\graphicspath{{images/4456}{images}}
|
||||
|
||||
\title{4456 Synthesizer Mirny / 4457 HF Synthesizer Mirny + Almazny}
|
||||
\title{4456 Synthesizer Mirny}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2025}
|
||||
\revision{Revision 2}
|
||||
\date{January 2022}
|
||||
\revision{Revision 1}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -13,27 +13,29 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{4-channel wide-band PLL/VCO-based microwave frequency synthesiser}
|
||||
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz for 4456 Mirny only}
|
||||
\item{Up to 12 GHz with 4457 Almazny}
|
||||
\item{Higher frequency resolution than 4410/4412 Urukul}
|
||||
\item{Lower jitter, phase noise than 4410/4412 Urukul}
|
||||
\item{4-channel VCO/PLL}
|
||||
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz}
|
||||
\item{Up to 13.6 GHz with Almazny mezzanine}
|
||||
\item{Higher frequency resolution than Urukul}
|
||||
\item{Lower jitter and phase noise}
|
||||
\item{Large frequency changes take several milliseconds}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Low-noise microwave source}
|
||||
\item{Quantum state control}
|
||||
\item{Driving acousto/electro-optic modulators}
|
||||
\item{Low-noise microwave source}
|
||||
\item{Quantum state control}
|
||||
\item{Driving acousto/electro-optic modulators}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 4456 Synthesizer Mirny card is a 4hp EEM module; the 4457 HF Synthesizer Mirny + Almazny card, consisting of 4456 Mirny plus the 4-channel Almazny HF mezzanine, is a 8hp EEM module. Both Synthesizer cards add microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
The 4456 Synthesizer Mirny card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
Both cards provide 4 channels of PLL frequency synthesis. 4456 Synthesizer Mirny supports output frequencies from 53 MHz to \textgreater 4GHz. As 4457 HF Synthesizer with Almazny mezzanine this range is expanded up to 12 GHz.
|
||||
It provides 4 channels of PLL frequency synthesis. Output frequencies from 53 MHz to \textgreater 4 GHz are supported.The range can be expanded up to 13.6 GHz with the Almazny mezzanine (4467 HF Synthesizer).
|
||||
|
||||
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provides at least 50 dB isolation.
|
||||
|
||||
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provide at least 50 dB isolation.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
@ -273,230 +275,158 @@
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=2in]{photo4457.jpg}
|
||||
\caption{Mirny + Almazny card}
|
||||
\includegraphics[height=2in]{photo4456.jpg}
|
||||
\includegraphics[height=3in, angle=90]{Mirny_FP.pdf}
|
||||
\caption{Mirny card and front panel}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\subfloat[\centering Mirny and Almazny front panels]{{
|
||||
\begin{minipage}[b]{0.5\linewidth}
|
||||
\centering
|
||||
\includegraphics[height=3in, angle=90]{fp4456.pdf} \\
|
||||
\vspace{0.2in}
|
||||
\includegraphics[height=3in, angle=90]{fp4457.pdf}
|
||||
\vspace{0.25in}
|
||||
\end{minipage}
|
||||
}}
|
||||
\subfloat[\centering Mirny, top-down view]{{
|
||||
\includegraphics[height=2.5in]{photo4456.jpg}
|
||||
}}
|
||||
\end{figure}
|
||||
|
||||
\sourcesectiond{4456 Synthesizer Mirny}{the 4457 Almazny mezzanine}{https://github.com/sinara-hw/mirny}{https://github.com/sinara-hw/Almazny}
|
||||
\sourcesection{4456 Synthesizer Mirny}{https://github.com/sinara-hw/mirny}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
Specifications of parameters are based on the datasheets of the PLL IC
|
||||
(ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}} for 4456 Mirny, ADF5355\footnote{\label{adf5355}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5355.pdf}}) for 4457 Almazny),
|
||||
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}}),
|
||||
and digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}).
|
||||
Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}\url{https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}}.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
% Note to future editors, the clk_div signal in gateware is not used.
|
||||
% Input divider was removed (mirny#8)
|
||||
Clock input & & & & & \\
|
||||
\hspace{3mm}Frequency\repeatfootnote{adf5356}
|
||||
& 10 & & 250 & MHz & Single-ended clock input (PLL config.) \\
|
||||
& 10 & & 600 & MHz & Differential clock input (PLL config.) \\
|
||||
\cline{2-6}
|
||||
\hspace{3mm}Differential input swing\repeatfootnote{clock_buffer}
|
||||
& 0.11 & & 1.55 & V\textsubscript{p-p} & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Output Specifications}
|
||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Frequency & 53.125 & & 4000 & MHz & 4456 Mirny only \\
|
||||
& & & 12000 & MHz & With Almazny mezzanine \\
|
||||
\hline
|
||||
Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
|
||||
\hline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
Specifications of parameters are based on the datasheets of the PLL IC
|
||||
(ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}}),
|
||||
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}}),
|
||||
and digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}).
|
||||
Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}\url{https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}}.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Output Specifications, cont.}
|
||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Lock time & & 1.7 & & ms & 4456 Mirny channels \\
|
||||
& & 3.5 & & ms & 4457 Almazny channels \\
|
||||
\hline
|
||||
Resolution & & & & \\
|
||||
\hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{3}{c|}{52} & bits & \\
|
||||
\hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{3}{c|}{24} & bits & \\
|
||||
\hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{3}{c|}{0.5} & dB & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
% Note to future editors, the clk_div signal in gateware is not used.
|
||||
% Input divider was removed (mirny#8)
|
||||
Clock input & & & & & \\
|
||||
\hspace{3mm}Frequency\repeatfootnote{adf5356}
|
||||
& 10 & & 250 & MHz & Single-ended clock input (PLL config.) \\
|
||||
& 10 & & 600 & MHz & Differential clock input (PLL config.) \\
|
||||
\cline{2-6}
|
||||
\hspace{3mm}Differential input swing\repeatfootnote{clock_buffer}
|
||||
& 0.11 & & 1.55 & V\textsubscript{p-p} & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
Phase noise performance of 4456 Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. 4456 Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
|
||||
|
||||
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[height=3in]{mirny_phase_noise_cm_choke.png}
|
||||
\caption{Phase noise measurement at 1 GHz}
|
||||
\end{figure}
|
||||
|
||||
\begin{itemize}
|
||||
\item Red: Before any modifications
|
||||
\item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
|
||||
\end{itemize}
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Output Specifications}
|
||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Frequency & 53.125 & & 4000 & MHz & \\
|
||||
\hline
|
||||
Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
|
||||
\hline
|
||||
Resolution & \multicolumn{4}{c|}{} & \\
|
||||
\hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{4}{c|}{52 bits} & \\
|
||||
\hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{4}{c|}{24 bits} & \\
|
||||
\hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{4}{c|}{0.5 dB} & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
|
||||
Phase noise at different output frequencies is then measured:
|
||||
Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
|
||||
|
||||
\newcolumntype{Y}{>{\centering\arraybackslash}X}
|
||||
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
|
||||
\begin{itemize}
|
||||
\item Red: Before any modifications
|
||||
\item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
|
||||
\end{itemize}
|
||||
|
||||
\begin{table}[hbt!]
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Phase noise performance}
|
||||
\begin{tabularx}{0.8\textwidth}{| c | Y | Y | Y | Y | Y |}
|
||||
\thickhline
|
||||
\multirow{2}{*}{\textbf{Output frequency}} &
|
||||
\multicolumn{5}{c|}{\textbf{Phase noise (dBc/Hz) at carrier offset}}\\
|
||||
\cline{2-6} & 1 kHz & 10 kHz & 100 kHz & 1 MHz & 10 MHz \\
|
||||
\hline
|
||||
125 MHz & -114 & -116 & -115 & -132 & -133 \\
|
||||
\hline
|
||||
500 MHz & -107 & -129 & -111 & -130 & -132 \\
|
||||
\hline
|
||||
1 GHz & -102 & -106 & -107 & -125 & -133 \\
|
||||
\hline
|
||||
2 GHz & -102 & -98 & -104 & -123 & -124 \\
|
||||
\hline
|
||||
3.5 GHz & -96 & -101 & -103 & -127 & -128 \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\includegraphics[height=3in]{mirny_phase_noise_cm_choke.png}
|
||||
\caption{Phase noise measurement at 1 GHz}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[height=3in]{mirny_phase_noise_frequency.png}
|
||||
\caption{Phase noise measurement}
|
||||
\end{figure}
|
||||
Phase noise at different output frequencies is then measured:
|
||||
|
||||
\section{Programmable LEDs}
|
||||
\newcolumntype{Y}{>{\centering\arraybackslash}X}
|
||||
|
||||
4456 Mirny features several status LEDs, including a two per output channel. One per channel displays RF switch status.
|
||||
|
||||
The 4457 Almazny mezzanine features an additional row of LEDs, one per output channel, without a fixed purpose. The associated ARTIQ module allows programming these directly through the channel \texttt{set} method.
|
||||
\begin{table}[hbt!]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Phase noise performance}
|
||||
\begin{tabularx}{0.8\textwidth}{| c | Y | Y | Y | Y | Y |}
|
||||
\thickhline
|
||||
\multirow{2}{*}{\textbf{Output frequency}} &
|
||||
\multicolumn{5}{c|}{\textbf{Phase noise (dBc/Hz) at carrier offset}}\\
|
||||
\cline{2-6} & 1 kHz & 10 kHz & 100 kHz & 1 MHz & 10 MHz \\
|
||||
\hline
|
||||
125 MHz & -114 & -116 & -115 & -132 & -133 \\
|
||||
\hline
|
||||
500 MHz & -107 & -129 & -111 & -130 & -132 \\
|
||||
\hline
|
||||
1 GHz & -102 & -106 & -107 & -125 & -133 \\
|
||||
\hline
|
||||
2 GHz & -102 & -98 & -104 & -123 & -124 \\
|
||||
\hline
|
||||
3.5 GHz & -96 & -101 & -103 & -127 & -128 \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
\sysdescsection
|
||||
|
||||
4456 Synthesizer Mirny must be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[height=3in]{mirny_phase_noise_frequency.png}
|
||||
\caption{Phase noise measurement}
|
||||
\end{figure}
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "mirny",
|
||||
"ports": 0,
|
||||
"clk_sel": "mmcx", // optional
|
||||
"refclk": 125e6 // optional
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
\codesection{4456 Synthesizer Mirny}
|
||||
|
||||
Replace 0 with the EEM port number used on the core device. Any port can be used. The \texttt{clk\_sel} field is optional and may be specified as one of either \texttt{xo}, \texttt{mmcx}, or \texttt{sma}. The default is \texttt{xo}. The \texttt{refclk} field is optional and the default is \texttt{100e6}.
|
||||
\subsection{1 GHz sinusoidal wave}
|
||||
Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.
|
||||
|
||||
For 4457 Mirny + Almazny, one field must be added:
|
||||
\inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "mirny",
|
||||
"almazny": true,
|
||||
"ports": 0
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
\subsection{ADF5356 power control}
|
||||
Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:
|
||||
|
||||
\codesection{4456 Synthesizer Mirny and 4457 Mirny + Almazny}
|
||||
\inputcolorboxminted{firstline=28,lastline=28}{examples/pll.py}
|
||||
|
||||
\subsection{1 GHz sinusoidal wave}
|
||||
Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.
|
||||
The parameter corresponds to a specific change of output power according to the following table\repeatfootnote{adf5356}.
|
||||
|
||||
\inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
|
||||
\begin{center}
|
||||
\captionof{table}{Power changes from ADF5356}
|
||||
\begin{tabular}{|c|c|}
|
||||
\hline
|
||||
Parameter & Power \\ \hline
|
||||
0 & -4 dBm \\ \hline
|
||||
1 & -1 dBm \\ \hline
|
||||
2 & +2 dBm \\ \hline
|
||||
3 & +5 dBm \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
\subsection{Almazny paired output}
|
||||
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the following line"
|
||||
|
||||
Mirny and Almazny output channels are paired, and Almazny output channels output twice the frequency of the main Mirny outputs. To set Almazny HF outputs for 4457 HF Synthesizer, set the Mirny outputs to one-half the desired frequency. The above code, run with 4457 HF Synthesizer, will also output 2GHz from Almazny HF0.
|
||||
\inputcolorboxminted{firstline=29,lastline=29}{examples/pll.py}
|
||||
|
||||
\subsection{ADF5356 power control}
|
||||
Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:
|
||||
\subsection{Periodic 100\textmu s pulses}
|
||||
The output can be toggled on and off periodically using the RF switches. The following code emits a 100\textmu s pulse in every millisecond. A microwave signal should be programmed in prior (such as the 1 GHz wave example).
|
||||
|
||||
\inputcolorboxminted{firstline=28,lastline=28}{examples/pll.py}
|
||||
\inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
|
||||
|
||||
The parameter corresponds to a specific change of output power according to the following table\repeatfootnote{adf5356}.
|
||||
|
||||
\begin{center}
|
||||
\captionof{table}{Power changes from ADF5356}
|
||||
\begin{tabular}{|c|c|}
|
||||
\hline
|
||||
Parameter & Power \\ \hline
|
||||
0 & -4 dBm \\ \hline
|
||||
1 & -1 dBm \\ \hline
|
||||
2 & +2 dBm \\ \hline
|
||||
3 & +5 dBm \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the following line"
|
||||
|
||||
\inputcolorboxminted{firstline=29,lastline=29}{examples/pll.py}
|
||||
|
||||
\subsection{Periodic 100\textmu s pulses}
|
||||
The output can be toggled on and off periodically using the RF switches. The following code emits a 100\textmu s pulse in every millisecond. A microwave signal should be programmed in prior (such as the 1 GHz wave example).
|
||||
|
||||
\inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
|
||||
|
||||
\ordersection{4456 Synthesizer Mirny or 4457 HF Synthesizer Mirny + Almazny}
|
||||
\ordersection{4456 Synthesizer Mirny}
|
||||
|
||||
\finalfootnote
|
||||
|
||||
99
examples/unsorted
Normal file
99
examples/unsorted
Normal file
@ -0,0 +1,99 @@
|
||||
from artiq.experiment import *
|
||||
|
||||
class SineWave(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
|
||||
self.leds = dict()
|
||||
self.ttl_outs = dict()
|
||||
|
||||
self.dacs_config = dict()
|
||||
self.dac_volt = dict()
|
||||
self.dac_dds = dict()
|
||||
self.dac_trigger = dict()
|
||||
|
||||
ddb = self.get_device_db()
|
||||
for name, desc in ddb.items():
|
||||
if isinstance(desc, dict) and desc["type"] == "local":
|
||||
module, cls = desc["module"], desc["class"]
|
||||
if (module, cls) == ("artiq.coredevice.ttl", "TTLOut"):
|
||||
dev = self.get_device(name)
|
||||
if "led" in name:
|
||||
self.leds[name] = dev
|
||||
else:
|
||||
self.ttl_outs[name] = dev
|
||||
|
||||
if (module, cls) == ("artiq.coredevice.shuttler", "Config"):
|
||||
dev = self.get_device(name)
|
||||
self.dacs_config[name] = dev
|
||||
|
||||
if (module, cls) == ("artiq.coredevice.shuttler", "Volt"):
|
||||
dev = self.get_device(name)
|
||||
self.dac_volt[name] = dev
|
||||
|
||||
if (module, cls) == ("artiq.coredevice.shuttler", "Dds"):
|
||||
dev = self.get_device(name)
|
||||
self.dac_dds[name] = dev
|
||||
|
||||
if (module, cls) == ("artiq.coredevice.shuttler", "Trigger"):
|
||||
dev = self.get_device(name)
|
||||
self.dac_trigger[name] = dev
|
||||
|
||||
|
||||
self.leds = sorted(self.leds.items(), key=lambda x: x[1].channel)
|
||||
self.ttl_outs = sorted(self.ttl_outs.items(), key=lambda x: x[1].channel)
|
||||
|
||||
self.dacs_config = sorted(self.dacs_config.items(), key=lambda x: x[1].channel)
|
||||
self.dac_volt = sorted(self.dac_volt.items(), key=lambda x: x[1].channel)
|
||||
self.dac_dds = sorted(self.dac_dds.items(), key=lambda x: x[1].channel)
|
||||
self.dac_trigger = sorted(self.dac_trigger.items(), key=lambda x: x[1].channel)
|
||||
|
||||
|
||||
@kernel
|
||||
def set_dac_config(self, config):
|
||||
config.set_config(0xFFFF)
|
||||
|
||||
@kernel
|
||||
def set_test_dac_volt(self, volt):
|
||||
a0 = 0
|
||||
a1 = 0
|
||||
a2 = 0
|
||||
a3 = 0
|
||||
volt.set_waveform(a0, a1, a2, a3)
|
||||
|
||||
|
||||
@kernel
|
||||
def set_test_dac_dds(self, dds):
|
||||
b0 = 0x0FFF
|
||||
b1 = 0
|
||||
b2 = 0
|
||||
b3 = 0
|
||||
c0 = 0
|
||||
c1 = 0x147AE148 # Frequency = 10MHz
|
||||
c2 = 0
|
||||
dds.set_waveform(b0, b1, b2, b3, c0, c1, c2)
|
||||
|
||||
@kernel
|
||||
def set_dac_trigger(self, trigger):
|
||||
trigger.trigger(0xFFFF)
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
self.core.reset()
|
||||
|
||||
self.core.break_realtime()
|
||||
t = now_mu() - self.core.seconds_to_mu(0.2)
|
||||
while self.core.get_rtio_counter_mu() < t:
|
||||
pass
|
||||
|
||||
for dac_config_name, dac_config_dev in self.dacs_config:
|
||||
self.set_dac_config(dac_config_dev)
|
||||
|
||||
for dac_volt_name, dac_volt_dev in self.dac_volt:
|
||||
self.set_test_dac_volt(dac_volt_dev)
|
||||
|
||||
for dac_dds_name, dac_dds_dev in self.dac_dds:
|
||||
self.set_test_dac_dds(dac_dds_dev)
|
||||
|
||||
for dac_trigger_name, dac_trigger_dev in self.dac_trigger:
|
||||
self.set_dac_trigger(dac_trigger_dev)
|
||||
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Loading…
Reference in New Issue
Block a user