Makefile/flake.nix: use latexmk

.gitignore

@@ -1,9 +1,11 @@
 *.out
-*.log
 *.aux
+*.fls
+*.fdb_latexmk
 
 _minted-*
 build
 result
 
 images/unsorted
+examples/unsorted

1124.tex

@@ -4,8 +4,8 @@
 
 \title{1124 Carrier Kasli 2.0}
 \author{M-Labs Limited}
-\date{October 2024}
-\revision{Revision 2}
+\date{April 2025}
+\revision{Revision 3}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -160,7 +160,7 @@
 
 \begin{figure}[hbt!]
     \centering
-    \includegraphics[angle=90,height=0.9in]{Kasli_FP.pdf}
+    \includegraphics[angle=90,height=0.9in]{fp1124.jpg}
     \caption{Kasli 2.0 front panel}
 \end{figure}
 

1125.tex

@@ -4,8 +4,8 @@
 
 \title{1125 Carrier Kasli-SoC}
 \author{M-Labs Limited}
-\date{December 2024}
-\revision{Revision 1} % potentially publishable pending whether block diagram is necessary
+\date{April 2025}
+\revision{Revision 2}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -47,7 +47,11 @@
     \centering
     \includegraphics[height=3in]{photo1125.jpg}
     \caption{Kasli-SoC card}
-    \includegraphics[angle=90,height=1in]{Kasli-SoC_FP.pdf}
+\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[angle=90,height=1in]{fp1125.jpg}
     \caption{Kasli-SoC front panel}
 \end{figure}
 
@@ -107,7 +111,7 @@
 
     \begin{figure}[hbt!]
         \centering
-        \includegraphics[height=3in]{kasli-soc_dip_switches.jpg}
+        \includegraphics[height=3in]{kasli_soc_dip_switches.jpg}
         \caption{Position of DIP switches, SD card, and reset pins}
     \end{figure}
 

1550.tex

@@ -0,0 +1,250 @@
+\input{preamble.tex}
+\graphicspath{{images}, {images/1550}}
+
+\title{1550 Laser Diode Driver Kirdy}
+\author{M-Labs Limited}
+\date{April 2025}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+    \begin{itemize}
+        \item{307.2 mA max output current, 20-bit resolution}
+        \item{Low noise current source, 300 pA/rtHz @ 1 kHz}
+        \item{Modulation input with DC-18 MHz bandwidth}
+        \item{Monitor photodiode and LD protection}
+        \item{Temperature controller with sub-mK stability}
+        \item{Full digital control over Ethernet}
+        \item{Bias-tee for RF modulation input}
+    \end{itemize}
+
+\section{Applications}
+
+    \begin{itemize}
+        \item{Spectroscopy}
+        \item{Laser cooling}
+        \item{Atomic clocks}
+        \item{Suitable for use with adapter and preinstalled laser assembly or with external laser heads}
+    \end{itemize}
+
+\section{General Description}
+
+    The 1550 Laser Diode Driver Kirdy is an 8hp EEM module, part of the Sinara open hardware family. It serves as a precision laser diode driver, featuring a low-noise current source, low- and high-frequency modulation inputs, and full digital control over Ethernet. Soft start, laser power monitoring with a user-defined trip point, overtemperature protection, and a protection relay minimize the risk of damage to the laser diode.
+
+    1550 Kirdy supports both low-frequency modulation, suitable for laser locks and linewidth reduction, as well as RF modulation injected directly into the diode, typically to add sidebands to the optical output and implement stabilization schemes such as Pound-Drever-Hall and modulation transfer spectroscopy.
+
+% Switch to next column
+\vfill\break
+
+%\begin{figure}[h]
+%    \centering
+%    \scalebox{1.15}{
+%    \begin{circuitikz}[european, every label/.append style={align=center}]
+%        \begin{scope}[]
+%            % if applicable
+%        \end{scope}
+%    \end{circuitikz}
+%    }
+%
+%    \caption{Simplified Block Diagram}
+%\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2.5in]{photo1550.jpg}
+    \caption{Kirdy card photo}
+    \includegraphics[height=3in, angle=90]{fp1550.pdf}
+    \caption{Kirdy front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{1550 Laser Diode Driver Kirdy}{https://git.m-labs.hk/sinara-hw/kirdy} The associated adapter can be found at the repository \url{https://git.m-labs.hk/sinara-hw/kirdyAdapter/src/branch/master}.
+
+\section{Electrical Specifications}
+
+    These specifications are based upon various information from the Sinara hardware repository\footnote{\label{repo}\url{https://git.m-labs.hk/sinara-hw/kirdy/}}.
+
+    \begin{table}[hbt!]
+        \centering
+        \begin{threeparttable}
+        \caption{Recommended Operating Conditions}
+        \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \hline
+            Input power & & & & & \\
+            \hspace{3mm} Voltage & & 12 & & V \\
+            \hspace{3mm} Current & & & 2.0 & A & \\
+            \hline
+            LF modulation input\textdagger & & & & & \\
+            \hspace{3mm} Voltage & -1 & & 1 & V \\
+            \hspace{3mm} Bandwidth (-3 dB) & & 18 & & MHz & \\
+            \hspace{3mm} Impedance & & 50 / 43.3k & & $\Omega$ & Termination switch on/off \\
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
+    1550 Kirdy supports Power-over-Ethernet, PoE+ (802.3at) and PoE (802.3af) standards. Alternatively, power can be provided via input in front panel. When using PoE, TEC output current should be limited to ±2A.
+
+    \begin{table}[hbt!]
+        \centering
+        \begin{threeparttable}
+        \caption{Electrical Specifications}
+        \begin{tabularx}{\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \hline
+            Photodiode\textdagger & & & & & \\
+            \hspace{3mm} Photocurrent range & 0 & & 3.0 & mA & \\
+            \hspace{3mm} Photocurrent resolution & & 0.8 & & μA & \\
+            \hspace{3mm} Bandwidth (-3 dB) & & 500 & & Hz & \\
+            \hline
+            Laser diode current driver & & & & & \\
+            \hspace{3mm} Resolution & & 0.292 & & μA & \\
+            \hspace{3mm} Control range & & & 307.2 & mA & \\
+            \hspace{3mm} Current limit & & 319 & & mA & \\
+            \hspace{3mm} Compliance & 4.928 & & & V & \\
+            \hspace{3mm} Current noise @ 1 kHz & & & 300 & pA/rtHz & 300 mA DC bias, 10 $\Omega$ load \\
+            \hspace{3mm} RMS noise @ 10 Hz-1 MHz & & & 300 & nA & 300 mA DC bias, 10 $\Omega$ load \\
+            \hspace{3mm} Temp. coefficient & -1 & & +1 & ppm/°C & 50 mA DC bias, tested 43-56 °C \\
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
+    \textdagger Circuit may be damaged if photodiode input current exceeds 3.0 mA. It is possible to modify the circuit and reprogram the photodiode current monitor range in the Kirdy driver.
+
+\newpage
+
+    \begin{table}[hbt!]
+        \centering
+        \begin{threeparttable}
+        \caption{Electrical Specifications, cont.}
+        \begin{tabularx}{\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \thickhline
+            PID temperature controller & & & & & \\
+            \hspace{3mm} Stability & & 1 & & mK & with Kirdy adapter, copper plate; \mbox{subject} to operating conditions \\
+            \hline
+            TEC output & & & & & \\
+            \hspace{3mm} Resolution & & 22.9 & & μA & \\
+            \hspace{3mm} Control range & -3.0 & & 3.0 & A & 12 V power, active cooling \\
+                & -2.0 & & 2.0 & A & with PoE (802.3af) \\
+            \hspace{3mm} Compliance & & 4.3 & & V & \\
+            \hspace{3mm} Voltage reading resolution & & 3.22 & & mV & \\
+            \hspace{3mm} Current reading resolution & & 2.9 & & mA & \\
+            \hline
+            TEC limits & & & & \\
+            \hspace{3mm} Voltage limit range & 0 & & 4.3 & V & \\
+            \hspace{3mm} Voltage limit resolution & & 3.14 & & mV & \\
+            \hspace{3mm} Current limit range & -3.0 & & 3.0 & A & \\
+            \hspace{3mm} Current limit resolution & & 1.57 & & mA & \\
+            \hline
+            NTC thermistor sensor & & & & \\
+            \hspace{3mm} Resolution & & 0.01 & & mK & 10 k$\Omega$, B-constant 3950K, $T_{0}$ 25°C \\
+            \hspace{3mm} Sampling rate & & 16.67 & $>$1000 & Hz & Subject to operating conditions \\
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
+\section{Modulation inputs}
+
+    1550 Kirdy supports two additional modulation inputs via SMA in the front panel, respectively \texttt{HF MOD} for high-frequency and \texttt{LF MOD} for low-frequency. LF modulation input can accept DC input to impose a DC offset on the output current. HF modulation input is AC-coupled and acts as a bias-tee.
+
+    The relationship of modulation input to output current is governed by the following equation:
+
+    \[I_{L} = max(I_{D} + U_{in} \cdot G_{mod}, 0)\]
+
+    where $I_{L}$ is the laser diode current, $I_{D}$ is the laser diode driver output current, $U_{in}$ is the input voltage, and $G_{mod}$ is the modulation gain. Care should be taken that $I_{L}$ always remains under the current limit. Otherwise, overcurrent protection may be triggered.
+
+\newpage
+
+    Modulation gain is adjustable by DIP switch in top right of board. \textit{Exactly one} DIP switch should be enabled at all times. Enabling zero DIP switches may cause serious damage to the laser diode. Other configurations (multiple switches enabled) are invalid, but will not cause damage.
+
+    \begin{multicols}{2}
+
+        \centering
+        \vspace*{10pt}
+        \begin{tabular}{|l|c|}
+            \hline
+            \textbf{Switch} & \textbf{Setting} \\
+            \thickhline
+            1 & 25 mA/V \\
+            2 & 2.5 mA/V \\
+            3 & 0.25 mA/V \\
+            \thickhline
+        \end{tabular}
+        \captionof{table}{DIP switch settings}
+
+    \columnbreak
+
+        \centering
+        \includegraphics[height=1.5in]{kirdy_mod_switch.jpg}
+        \captionof{figure}{Position of DIP switch}
+
+    \end{multicols}
+
+    \begin{multicols}{2}
+
+\section{Configuring termination}
+
+    LF modulation input termination must be configured by setting a physical switch on the board. The termination DIP switch is found at the upper left part of the board, behind the front panel. Turning this switch on adds a 50 $\Omega$ termination to the LF modulation input. Without the switch, the input impedance is approximately 43.4k $\Omega$.
+
+    \vspace*{20pt}
+
+    \columnbreak
+
+        \centering
+        \includegraphics[height=1.5in]{kirdy_imp_switch.jpg}
+        \captionof{figure}{Position of DIP switch}
+
+    \end{multicols}
+
+
+\section{Adapter and Laser Options}
+
+    An optional adapter allows compact lasers in butterfly packages to be mounted directly onto 1550 Kirdy, with a fibre-optic output in the front panel. Multiple single-frequency narrow-linewidth lasers are currently available as preinstalled options for order.
+
+    Alternatively, Kirdy accepts laser signals broken out to the front panel and is suitable for use in driving external laser heads, including commercial or custom ECDLs (with additional piezo driver not included with Kirdy) or injection-locked Fabry-Perot diodes.
+
+\section{Firmware and driver}
+
+    1550 Kirdy features front panel Ethernet and USB-C. Either DFU or OpenOCD can be used to flash firmware; OpenOCD however requires a JTAG adapter.
+
+    Using M-Labs firmware, communication with a host system is performed over Ethernet/TCP in the form of predefined JSON objects. A Python driver implementing these can be found in the Kirdy firmware repo, hosted at \url{https://git.m-labs.hk/M-Labs/kirdy/}, under \texttt{pykirdy}. See inline documentation for descriptions of particular functions and implemented capabilities.
+
+    This driver may be used directly or through the Kirdy GUI, hosted in the same repo. To start the GUI, run the file \texttt{pykirdy/pykirdy/kirdy\_qt.py}, or install it using \texttt{pykirdy/pyproject.toml}. Users familiar with the Nix package manager through ARTIQ or for other reasons may note that the root of the repository includes a \texttt{flake.nix} with an appropriate development shell (e.g. \texttt{nix develop}) including all dependencies.
+
+    Examples in the \texttt{pykirdy} folder further demonstrate the use of the Kirdy driver, as well as the PID autotune temperature regulation feature.
+
+\newpage
+
+    \begin{figure}[hbt!]
+        \centering
+        \includegraphics[width=\textwidth]{kirdy_gui.jpg}
+        \caption{Kirdy driver GUI}
+    \end{figure}
+
+    To first connect to Kirdy, use the "Connect" button in the lower right corner and the IP address and port number assigned to Kirdy. By default, these are \texttt{192.168.1.128} and \texttt{1550} respectively. They can also be changed using commands supplied by the Python driver.
+
+
+\ordersection{1550 Laser Diode Driver Kirdy}
+
+    Kirdy can ship with a single-frequency narrow-linewidth laser pre-mounted and configured. Current wavelength options include 1270-1610 nm and 633-1064 nm. See the M-Labs hardware selection tool or contact M-Labs for prices and details.
+
+\finalfootnote
+
+\end{document}

2238.tex

@@ -439,7 +439,7 @@
     \centering
     \includegraphics[height=2in]{photo2238.jpg}
     \caption{MCX-TTL card}
-    \includegraphics[angle=90, height=0.6in]{fp2238.pdf}
+    \includegraphics[angle=90, height=0.5in]{fp2238.jpg}
     \caption{MCX-TTL front panel}
 \end{figure}
 

4410-4412.tex

@@ -888,7 +888,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
 
     4410/4412 DDS Urukul cards can operate with either a single or double EEM connections. When only EEM0 is connected, the card will act in single-EEM mode; when both EEM0 and EEM1 are connected, the card will act in double-EEM mode.
 
-    Double-EEM mode additionally provides 1 ns temporal resolution RF switches. Without EEM1, the only way to access the switches is through the CPLD, using SPI. With EEM1, RF switches can be controlled as a TTL output through the LVDS transceiver. 1 ns temporal resolution can then be achieved using the ARTIQ RTIO system. Double-EEM mode is also recommended for the SUServo configuration.
+    Double-EEM mode additionally provides 1 ns temporal resolution RF switches and multi-chip synchronisation. Without EEM1, the only way to access the switches is through the CPLD, using SPI. With EEM1, RF switches can be controlled as a TTL output through the LVDS transceiver. 1 ns temporal resolution can then be achieved using the ARTIQ RTIO system. Double-EEM mode is also recommended for the SUServo configuration.
 
 \sysdescsection
 

4456-4457.tex

@@ -3,8 +3,8 @@
 
 \title{4456 Synthesizer Mirny / 4457 HF Synthesizer Mirny + Almazny}
 \author{M-Labs Limited}
-\date{January 2025}
-\revision{Revision 2}
+\date{April 2025}
+\revision{Revision 3}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -285,10 +285,10 @@
     \subfloat[\centering Mirny and Almazny front panels]{{
         \begin{minipage}[b]{0.5\linewidth}
             \centering
-            \includegraphics[height=3in, angle=90]{fp4456.pdf} \\
-            \vspace{0.2in}
-            \includegraphics[height=3in, angle=90]{fp4457.pdf}
-            \vspace{0.25in}
+            \includegraphics[height=3.4in, angle=90]{fp4457.jpg} \\
+            \vspace{0.1in}
+            \includegraphics[height=3.4in, angle=90]{fp4456.jpg}
+            \vspace{0.3in}
         \end{minipage}
     }}
     \subfloat[\centering Mirny, top-down view]{{

5568.tex

@@ -3,8 +3,8 @@
 
 \title{5568 HD68-IDC}
 \author{M-Labs Limited}
-\date{January 2022}
-\revision{Revision 1}
+\date{April 2025}
+\revision{Revision 2}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -32,7 +32,7 @@
 \end{itemize}
 
 \section{General Description}
-The 5568 HD68-IDC card is a 4hp EEM module, part of the ARTIQ/Sinara family. It is an adapter card that converts IDC connections to or from HD68 connections. It can be connected via external HD68 cable to 5518 BNC-IDC or 5528 SMA-IDC cards.
+The 5568 HD68-IDC card is an 8hp EEM module, part of the ARTIQ/Sinara family. It is an adapter card that converts IDC connections to or from HD68 connections. It can be connected via external HD68 cable to 5518 BNC-IDC or 5528 SMA-IDC cards.
 
 Each card supports 32 channels, with one HD68 connector and four IDC connectors. Each IDC connector supports 8 channels. All 32 channels can be accessed using an external HD68 cable.
 
@@ -68,8 +68,8 @@ Each card supports 32 channels, with one HD68 connector and four IDC connectors.
 
 \begin{figure}[h]
     \centering
-    \includegraphics[height=3.5in, angle=90]{photo5568.jpg}
-    \includegraphics[height=3in, angle=90]{HD68_IDC_FP.pdf}
+    \includegraphics[height=3.1in, angle=90]{photo5568.jpg}
+    \includegraphics[height=2.5in, angle=90]{fp5568.jpg}
     \caption{Card and front panel}
 \end{figure}
 

5716.tex

@@ -0,0 +1,205 @@
+\input{preamble.tex}
+\input{shared/coredevice.tex}
+\graphicspath{{images}{images/5716}}
+
+\title{5716 DAC Shuttler}
+\author{M-Labs Limited}
+\date{January 2025}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+\begin{itemize}
+    \item{16-channel DAC}
+    \item{14-bit resolution, $<1$ LSB DNL}
+    \item{125 MSPS sample rate}
+    \item{Output voltage ±10 V}
+    \item{EEM FMC carrier with Artix-7 FPGA core}
+    \item{Remote analog front end card}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+    \item{Driving DC electrodes in ion traps}
+    \item{Ion chain splitting, ion shuttling}
+\end{itemize}
+
+\section{General Description}
+
+    The 5716 DAC Shuttler is an 8hp EEM module, shipped with associated remote analog front-end (AFE), part of the ARTIQ/Sinara family. It consists of the Shuttler FMC paired with an 8hp Sinara EEM FMC Carrier, which is capable of running as an ARTIQ satellite core through DRTIO-over-EEM. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+
+    ARTIQ gateware implements NIST PDQ-style waveform synthesizer which supports the use of sigma-delta modulation to increase effective resolution to 16 bits.
+
+    Digital communication between FMC and remote AFE is provided through mini-SAS HD cables. The AFE supports ±10 V output and 50 MHz 3dB bandwidth, using onboard 24-bit ADC for calibration.
+
+% Switch to next column
+\vfill\break
+
+%\begin{figure}[h]
+%    \centering
+%    \scalebox{1.15}{
+%    \begin{circuitikz}[european, every label/.append style={align=center}]
+%        \begin{scope}[]
+%            % if applicable
+%        \end{scope}
+%    \end{circuitikz}
+%    }
+%
+%    \caption{Simplified Block Diagram}
+%\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=1.7in, angle=-90]{photo5716.jpg}
+    \caption{Shuttler FMC}
+    \includegraphics[height=1.5in]{shuttler_afe.jpg}
+    \caption{Shuttler AFE}
+    \includegraphics[height=1.5in]{fmc_side.jpg}
+    \caption{Sinara EEM FMC carrier}
+    \includegraphics[height=2.5in, angle=90]{fp5716.jpg}
+    \caption{Shuttler front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{5716 DAC Shuttler}{https://github.com/sinara-hw/FMC_Shuttler} Files for the AFE card are stored at \url{https://github.com/sinara-hw/AFE_DAC_External}. Files for the Sinara EEM FMC Carrier can be found at \url{https://github.com/sinara-hw/EEM_FMC_Carrier}.
+
+\section{Electrical Specifications}
+
+    These specifications are based on the datasheet of the DAC IC (AD9117\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9114_9115_9116_9117.pdf}}), board measurements\footnote{\label{shuttler36}\url{https://github.com/sinara-hw/FMC_Shuttler/issues/36}}, and various information from the Sinara wiki\footnote{\label{wiki}\url{https://github.com/sinara-hw/FMC_Shuttler/wiki}}.
+
+    \begin{table}[h]
+        \centering
+        \begin{threeparttable}
+        \caption{Output Specifications}
+        \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            Sampling rate\repeatfootnote{wiki} & & 125 & & MSPS & \\
+            \hline
+            Output voltage\repeatfootnote{wiki} & -10 & & +10 & V & \\
+            \hline
+            Resolution\repeatfootnote{wiki} & & 14 & & bits & Raw \\
+                       & & 16 & & bits & With sigma-delta modulation \\
+            \hline
+            Settling time\repeatfootnote{dac} & & 11.5 & & ns & \\
+            \hline
+            Analog bandwidth\repeatfootnote{shuttler36} & & 12 & & MHz & \\
+            \hline
+            3dB bandwidth\repeatfootnote{wiki} & & 50 & & MHz & \\
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
+    Power to Shuttler is supplied over EEM. Power to the AFE is to be supplied over a 4-pin circular M8 connector placed between the mini-SAS HD ports. The AFE output port is 25-pin DSUB.
+
+\artiqsection
+
+    The Sinara EEM FMC Carrier features an XC7A200T-3FBG484E Xilinx Artix-7 FPGA, usually configured as an ARTIQ satellite core. Firmware and gateware for the Sinara EEM FMC Carrier is closely related to that used for 1124 Kasli 2.0 satellites. The specific binary generation target can be found in the module \texttt{artiq.gateware.targets.efc} of the ARTIQ repository.
+
+\newpage
+
+\sysdescsection
+
+    5716 Shuttler should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+        {
+            "type": "shuttler",
+            "ports": 0
+        }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 with the EEM port number used on the core device. Any port can be used. On the other side, the Sinara EEM FMC Carrier possesses two EEM ports, but only one is necessary for Shuttler. This should always be \texttt{EEM0}.
+
+    Since Shuttler acts as a DRTIO satellite, the DRTIO type of the core device should be specified as master, not standalone, even if no other satellite cores are used. DRTIO-over-EEM for Shuttler is automatically assigned a destination number, \#4 on Kasli 2.0, \#5 on Kasli-SoC\footnote{i.e., in both cases, first available destination number after those associated with the core device's downstream SFP slots.}. Destination numbers count up correspondingly for additional Shuttlers. See the ARTIQ manual\footnote{\url{https://m-labs.hk/artiq/manual/using_drtio_subkernels.html}} for instructions on configuring a routing table, for cases where you need one (for example, a Shuttler on a DRTIO satellite).
+
+\section{Clocking}
+
+    Clock input should be provided to Shuttler through the EEM FMC Carrier. The EEM FMC Carrier \textit{must} share a clock source with the associated core device. Clocks must be aligned to utilize DRTIO-over-EEM. Clock input can be provided to EEM FMC Carrier via SMA connector on front panel or MMCX connector at back of board (top right, above \texttt{EEM0}). The Shuttler FMC features a front panel MCX connector labeled for clock input; this is currently unused by ARTIQ firmware/gateware.
+
+    \begin{multicols}{2}
+        FMC Carrier clock source must be configured by setting the DIP switches on back of the board, under the following schema:
+
+        \begin{center}
+            \begin{tabular}{ | c | c | c | } \thickhline
+            \textbf{Clock Source} & \textbf{CLK\_SEL0} & \textbf{CLK\_SEL1} \\
+            \thickhline
+            Front panel SMA & 0 & 0 \\ \hline
+            Internal oscillator & 1 & 0 \\ \hline
+            Back MMCX & 0 & 1 \\ \hline
+            PE CLK & 1 & 1 \\ \hline
+            \end{tabular}
+        \end{center}
+
+        \vspace*{\fill}
+
+    \columnbreak
+
+        \begin{center}
+            \centering
+            \includegraphics[height=1.7in]{shuttler_dip_switches.jpg}
+            \captionof{figure}{Position of DIP switches}
+        \end{center}
+
+    \end{multicols}
+
+    Users should note that PE CLK and internal oscillator are not valid source choices for Shuttler.
+
+    At first power-up, FMC Carrier and connected core device will determine the clock skew over EEM transceiver and store the result in configuration memory. It can be accessed in ARTIQ under the key \texttt{eem\_drtio\_delay0} (where \texttt{0} is a counter that will be incremented for further DRTIO-over-EEM connections.)
+
+    If EEM cable or clocking cables are changed, or if either device is reflashed for any reason, this value must be manually erased in order to force a reevaluation of the clock skew. Either \texttt{artiq\_coremgmt config remove} (for original ARTIQ) or direct access to the SD card (on Zynq) should be used.
+
+\newpage
+
+\section{LEDs}
+
+    The EEM FMC Carrier provides two user LEDs, \texttt{L0} and \texttt{L1}, located on the front panel, which are accessible in ARTIQ gateware and can be used for testing.
+
+    The Shuttler AFE provides twenty LEDs in two banks. The four-LED bank to the right of the mini-SAS connectors indicate power status. The sixteen-LED bank to the left of the mini-SAS connectors indicate output relay status. DAC output is only valid when corresponding relay LEDs are on.
+
+\codesection{5716 DAC Shuttler}
+
+    Shuttler is capable of generating a waveform in the following equation:
+
+    \[ w(t) = a(t) + b(t) * cos(c(t)) \]
+
+    where $a(t)$ and $b(t)$ are cubic splines and $c(t)$ is a quadratic spline\footnote{See also the PDQ documentation hosted at the following link: \url{https://pdq.readthedocs.io/}}.
+
+    The following code initializes relay and ADC and resets all channels.
+
+    \inputcolorboxminted{firstline=21,lastline=42}{examples/shuttler.py}
+
+\newpage
+
+    \inputcolorboxminted{firstline=43,lastline=65}{examples/shuttler.py}
+
+    \subsection{Generating a basic waveform}
+
+    The following code generates a basic sine wave of approx 10 MHz on the \texttt{DAC0 I} channel. The value of \texttt{0x147AE148} used for $c_1$ sets the frequency as $c_1 / 2^{32} * 125$ MHz.
+
+    \inputcolorboxminted{firstline=67,lastline=85}{examples/shuttler.py}
+
+    \begin{figure}[!hbt]
+        \centering
+        \includegraphics[height=3in]{sine_wave.jpg}
+        \caption{Produced waveform, measured at \texttt{AFE0} output resistor R36A, R39A.}
+    \end{figure}
+
+    For more example waveforms see also the folder \texttt{kasli\_shuttler} in the ARTIQ \texttt{examples} directory.
+
+\ordersection{5716 DAC Shuttler}
+
+\finalfootnote
+
+\end{document}

6302.tex

@@ -3,8 +3,8 @@
 
 \title{6302 Grabber}
 \author{M-Labs Limited}
-\date{January 2025}
-\revision{Revision 0}
+\date{April 2025}
+\revision{Revision 1}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -50,9 +50,9 @@ The Sinara/ARTIQ stack supports defining rectangular ROIs (regions of interest);
 
 \begin{figure}[hbt!]
     \centering
-    \includegraphics[height=4in]{photo6302.jpg}
+    \includegraphics[height=3in, angle=-90]{photo6302.jpg}
     \caption{Grabber card}
-    \includegraphics[height=3in, angle=90]{fp6302.pdf}
+    \includegraphics[height=3in, angle=90]{fp6302.jpg}
     \caption{Grabber front panel}
 \end{figure}
 

7210.tex

@@ -3,8 +3,8 @@
 
 \title{7210 Clocker}
 \author{M-Labs Limited}
-\date{January 2024}
-\revision{Revision 3}
+\date{April 2025}
+\revision{Revision 4}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -219,7 +219,7 @@ Clocker can be powered externally or internally. To provide external power, conn
 \begin{figure}[hbt!]
     \centering
     \includegraphics[height=3.5in]{photo7210.jpg}
-    \includegraphics[height=3.5in]{clocker_front_panel.jpg}
+    \includegraphics[height=3.5in]{fp7210.jpg}
     \caption{Clocker card and front panel}
 \end{figure}
 

Makefile

@@ -1,13 +1,13 @@
-inputs = 1124 1125 2118-2128 2238 2245 4410-4412 4456 5108 5432 5518-5528 5568 7210
+inputs = 1008 1106 1124 1125 2118-2128 2238 2245 4410-4412 4456-4457 4624 5108 5432 5632 5633 5518-5528 5538 5568 6302 7210
 dir = build
 
 all: $(inputs)
 
 $(inputs) : % : %.tex
-	pdflatex -shell-escape $@.tex
+	latexmk -pdf -pdflatex="pdflatex -shell-escape" $@.tex
 	if ! test -d "$(dir)"; then mkdir build; fi
 	mv $@.pdf build/
 	rm $@.log
 
 clean:
-	rm -r _minted* *.aux *.out
+	rm -rf _minted* *.aux *out *.fls *.fdb_latexmk

examples/shuttler.py

@@ -0,0 +1,85 @@
+from artiq.experiment import *
+
+class SineWave(EnvExperiment):
+
+    def build(self):
+        self.setattr_device("core")
+        self.shuttler0_leds = (
+            [ self.get_device("shuttler0_led{}".format(i)) for i in range(2) ]
+        )
+        self.setattr_device("shuttler0_config")
+        self.setattr_device("shuttler0_trigger")
+        self.shuttler0_dcbias = (
+            [ self.get_device("shuttler0_dcbias{}".format(i)) for i in range(16) ]
+        )
+        self.shuttler0_dds = (
+            [ self.get_device("shuttler0_dds{}".format(i)) for i in range(16) ]
+        )
+        self.setattr_device("shuttler0_relay")
+        self.setattr_device("shuttler0_adc")
+
+    @kernel
+    def relay_init(self):
+        self.shuttler0_relay.init()
+        self.shuttler0_relay.enable(0x0000)
+
+    @kernel
+    def adc_init(self):
+        delay_mu(int64(self.core.ref_multiplier))
+        self.shuttler0_adc.power_up()
+
+        delay_mu(int64(self.core.ref_multiplier))
+        assert self.shuttler0_adc.read_id() >> 4 == 0x038d
+
+        delay_mu(int64(self.core.ref_multiplier))
+        # The actual output voltage is limited by the hardware,
+        # the calculated calibration gain and offset.
+        # For example, if the system has a calibration gain of
+        # 1.06, then the max output voltage = 10 / 1.06 = 9.43V.
+        # Setting a value larger than 9.43V will result in overflow.
+        self.shuttler0_adc.calibrate(
+            self.shuttler0_dcbias, self.shuttler0_trigger, self.shuttler0_config)
+
+    @kernel
+    def shuttler_channel_reset(self, ch):
+        self.shuttler0_dcbias[ch].set_waveform(
+            a0=0, a1=0, a2=0, a3=0,
+        )
+        self.shuttler0_dds[ch].set_waveform(
+            b0=0, b1=0, b2=0, b3=0,
+            c0=0, c1=0, c2=0,
+        )
+        self.shuttler0_trigger.trigger(1 << ch)
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+
+        self.relay_init()
+        self.adc_init()
+
+        for i in range(16):
+            self.shuttler_channel_reset(i)
+            # To avoid RTIO Underflow
+            delay(50*us)
+
+    @kernel
+    def sine(self):
+        for i in range(2):
+            self.shuttler0_dcbias[i].set_waveform(
+                a0=0,
+                a1=0,
+                a2=0,
+                a3=0,
+            )
+            self.shuttler0_dds[i].set_waveform(
+                b0=0x0FFF,
+                b1=0,
+                b2=0,
+                b3=0,
+                c0=0,
+                c1=0x147AE148, # Frequency = 10MHz
+                c2=0,
+            )
+        self.shuttler0_trigger.trigger(0xFFFF)

flake.lock

@@ -2,16 +2,16 @@
   "nodes": {
     "nixpkgs": {
       "locked": {
-        "lastModified": 1729880355,
-        "narHash": "sha256-RP+OQ6koQQLX5nw0NmcDrzvGL8HDLnyXt/jHhL1jwjM=",
+        "lastModified": 1744440957,
+        "narHash": "sha256-FHlSkNqFmPxPJvy+6fNLaNeWnF1lZSgqVCl/eWaJRc4=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "18536bf04cd71abd345f9579158841376fdd0c5a",
+        "rev": "26d499fc9f1d567283d5d56fcf367edd815dba1d",
         "type": "github"
       },
       "original": {
         "owner": "NixOS",
-        "ref": "nixos-unstable",
+        "ref": "nixos-24.11",
         "repo": "nixpkgs",
         "type": "github"
       }

flake.nix

@@ -1,7 +1,7 @@
 {
   description = "Sinara datasheets";
 
-  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-unstable;
+  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.11;
 
   outputs = { self, nixpkgs }:
     let
@@ -24,10 +24,8 @@
         name = "datasheets-pdfs";
         src = self;
         buildInputs = [ latex-pkgs ] ++ python-pkgs;
-        # is there a better way to get .aux/.out files correct than to just run latexpdf twice?
         buildPhase = ''
           make all
-          make all
         '';
         installPhase = ''
           mkdir $out