ttls: formatting

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architeuthis 2025-01-24 14:56:59 +01:00
parent 47ce969445
commit 8e54d54b17
7 changed files with 538 additions and 517 deletions

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@ -295,11 +295,11 @@ Note that isolated TTL cards are less suited to low-noise applications as the is
\begin{figure}[hbt!]
\centering
\includegraphics[height=1.8in]{photo2118-2128.jpg }
\caption{BNC-TTL and SMA-TTL cards}%
\includegraphics[angle=90, height=0.7in]{DIO_BNC_FP.jpg}
\includegraphics[angle=90, height=0.4in]{DIO_SMA_FP.jpg}
\caption{BNC-TTL and SMA-TTL front panels}%
\label{fig:example}%
\caption{BNC-TTL and SMA-TTL cards}
\includegraphics[angle=90, height=0.7in]{fp2118.jpg}
\includegraphics[angle=90, height=0.4in]{fp2128.jpg}
\caption{BNC-TTL and SMA-TTL front panels}
\label{fig:example}
\end{figure}
\onecolumn
@ -396,6 +396,7 @@ IO direction and termination must be configured by setting physical switches on
\end{figure}
\newpage
\codesection{2118 BNC-TTL/2128 SMA-TTL cards}
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
@ -409,6 +410,7 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
\newpage
\subsection{Sub-coarse-RTIO-cycle pulse}
With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
@ -419,6 +421,7 @@ The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gat
The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
@ -427,6 +430,7 @@ Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
\newpage
\subsection{Edge counting using \texttt{EdgeCounter}}
This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
@ -444,6 +448,7 @@ Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel ca
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
\newpage
\subsection{Minimum sustained event separation}
The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.

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@ -439,7 +439,7 @@ Each channel supports 50\textOmega~terminations individually controllable using
\centering
\includegraphics[height=2in]{photo2238.jpg}
\caption{MCX-TTL card}
\includegraphics[angle=90, height=0.6in]{DIO_MCX_FP.pdf}
\includegraphics[angle=90, height=0.6in]{fp2238.pdf}
\caption{MCX-TTL front panel}
\end{figure}
@ -505,8 +505,11 @@ All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherw
\newpage
\section{Configuring IO Direction \& Termination}
IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
\begin{multicols}{2}
Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
\begin{itemize}
@ -516,15 +519,19 @@ Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note th
\item IO direction switch open (OFF) \\
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
\end{itemize}
\columnbreak
\begin{center}
\centering
\includegraphics[height=1.7in]{mcx_ttl_switches.jpg}
\captionof{figure}{Position of switches}
\end{center}
\end{multicols}
\newpage
\codesection{2238 MCX-TTL card}
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
@ -538,6 +545,7 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
\newpage
\subsection{Edge counting in an 1ms window}
The channel should be configured as input in both gateware and hardware.
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}

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@ -297,7 +297,7 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
\begin{figure}[hbt!]
\centering
\includegraphics[angle=90, height=1.7in]{photo2245.jpg}
\includegraphics[angle=90, height=0.4in]{DIO_RJ45_FP.pdf}
\includegraphics[angle=90, height=0.4in]{fp2245.pdf}
\caption{LVDS-TTL card and front panel}
\end{figure}
@ -389,7 +389,9 @@ All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 30
\newpage
\section{Configuring IO Direction \& Termination}
\begin{multicols}{2}
The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
\begin{itemize}
\itemsep0em
@ -400,11 +402,13 @@ The IO direction of each channel can be configured by DIP switches, which are fo
\end{itemize}
\vspace*{\fill}\columnbreak
\begin{center}
\centering
\includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
\captionof{figure}{Position of switches}
\end{center}
\end{multicols}
\newpage
@ -448,6 +452,7 @@ One channel needs to be configured as input, and the other as output.
\egroup}
\newpage
\subsection{SPI Master Device}
If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
\begin{enumerate}
@ -552,6 +557,7 @@ The direction switches on the LVDS-TTL card should be set to the correct IO dire
\end{center}
\newpage
\subsubsection{SPI Configuration}
The following examples will assume the SPI communication has the following properties:
\begin{itemize}
@ -591,6 +597,7 @@ Typically, an SPI write operation involves sending an instruction and data to th
\end{center}
\newpage
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
@ -620,6 +627,7 @@ Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This S
\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
\newpage
\ordersection{2245 LVDS-TTL}
\finalfootnote

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