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preamble: macro for code sections

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architeuthidae 2024-11-07 16:01:52 +01:00 committed by sb10q
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1124.tex
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@ -278,9 +278,7 @@ Kasli 2.0 supplies three user LEDs for debugging purposes. Two are located on th
\newpage \newpage
\section{Example ARTIQ Code} \section{Example ARTIQ Code}
The sections below demonstrate simple usage scenarios of extensions on the ARTIQ control system. These extensions make use of the resources on the Kasli 2.0 1124 carrier board. They do not exhaustively demonstrate all the features of the ARTIQ system. \codesection{Kasli 2.0 1124 carrier}
The full documentation for ARTIQ software and gateware, including the guide for its use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material on the functions and structures used here.
\subsection{Direct Memory Access (DMA)} \subsection{Direct Memory Access (DMA)}
Instead of directly emitting RTIO events, sequences of RTIO events can be recorded in advance and stored in the local SDRAM. The event sequence can then be replayed at a specified timestamp. This is of special advantage in cases where RTIO events are too closely placed to be generated as they are executed, as events can be replayed at a higher speed than the on-FPGA CPU alone is capable of. Instead of directly emitting RTIO events, sequences of RTIO events can be recorded in advance and stored in the local SDRAM. The event sequence can then be replayed at a specified timestamp. This is of special advantage in cases where RTIO events are too closely placed to be generated as they are executed, as events can be replayed at a higher speed than the on-FPGA CPU alone is capable of.

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preamble.tex
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@ -37,11 +37,23 @@
#1, like all the Sinara hardware family, is open-source hardware, and design files (schematics, PCB layouts, BOMs) can be found in detail at the repository \url{#2}. #1, like all the Sinara hardware family, is open-source hardware, and design files (schematics, PCB layouts, BOMs) can be found in detail at the repository \url{#2}.
} }
\newcommand*{\sourcesectiond}[4]{
\section{Source}
#1 and #2, like all the Sinara hardware family, are open-source hardware, and design files (schematics, PCB layouts,
BOMs) can be found in detail at the repositories \url{#3} and \url{#4}.
}
\newcommand*{\ordersection}[1]{ \newcommand*{\ordersection}[1]{
\section{Ordering Information} \section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and choose #1 in the ARTIQ/Sinara hardware selection tool. Cards can be ordered as part of a fully-featured ARTIQ/Sinara crate or standalone through the 'Spare cards' option. Otherwise, orders can also be made by writing directly to \url{mailto:sales@m-labs.hk}. To order, please visit \url{https://m-labs.hk} and choose #1 in the ARTIQ/Sinara hardware selection tool. Cards can be ordered as part of a fully-featured ARTIQ/Sinara crate or standalone through the 'Spare cards' option. Otherwise, orders can also be made by writing directly to \url{mailto:sales@m-labs.hk}.
} }
\newcommand{\codesection}[1] {
The sections below demonstrate simple usage scenarios of extensions on the ARTIQ control system. These extensions make use of the resources of the #1. They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for ARTIQ software and gateware, including the guide for its use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material of the functions and structures used here.
}
\newcommand*{\finalfootnote}{ \newcommand*{\finalfootnote}{
\section*{} \section*{}
\vspace*{\fill} \vspace*{\fill}