architeuthis/datasheets
1
0
Fork 0
forked from sinara-hw/datasheets
Code Pull Requests Activity

1124, 1125: fixes

Browse Source
This commit is contained in:
architeuthis 2024-12-14 21:13:25 +01:00
parent 0c26439099
commit 3bcff89526
3 changed files with 63 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
1124.tex
View File

@ -14,20 +14,20 @@
\section{Features}
\begin{itemize}
\item{4 SFP 6Gb/s slots for Ethernet and DRTIO}
\item{12 EEM ports for daughtercards}
\item{4 MMCX clock outputs}
\item{Xilinx Artix-7 FPGA core}
\item{DDR3 SDRAM}
\item{4 SFP 6Gb/s slots for Ethernet \& DRTIO at 2.5Gb/s}
\item{12 EEM ports for daughtercards}
\item{4 MMCX clock outputs}
\item{Xilinx Artix-7 FPGA core}
\item{DDR3 SDRAM}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Run ARTIQ kernels}
\item{Communicate with the host}
\item{Control other Sinara EEM cards}
\item{Distributed Real-Time I/O}
\item{Run ARTIQ kernels}
\item{Communicate with the host}
\item{Control other Sinara EEM cards}
\item{Distributed Real-Time I/O}
\end{itemize}
\section{General Description}
@ -173,33 +173,11 @@
\section{Electrical Specifications}
External clock parameters are derived based on the internal termination specified in
UG471\footnote{\label{ug471}\url{https://docs.xilinx.com/v/u/en-US/ug471\_7Series\_SelectIO}}
UG471\footnote{\label{ug471}\url{https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO}}
and the voltage range specified in
DS181\footnote{\label{ds181}\url{https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}}. These figures account for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}\url{https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}}).
\begin{table}[h]
\centering
\begin{threeparttable}
\caption{Recommended Operating Conditions}
\begin{tabularx}{0.85\textwidth}{l | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Clock input & & & & &\\
\hspace{3mm} Input frequency & & 125 & & MHz & Si5324 synthesizer bypassed \\
\cline{2-6}
% 100R termination & 100/350/600 mV differential input after the transformer.
& \multicolumn{3} {c|}{10/100/125} & MHz & RTIO clock synthesized from input \\
\cline{2-6}
\hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm & \\
\hline
Power supply rating & \multicolumn{4}{c|}{12V, 5A} & \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
Power is to be supplied through the barrel connector in the front panel, size 5.5 mm OD, 2.5 mm ID, and is passed on to daughtercards through the EEM connections. Locking barrel connectors are supported.
\spectable
\section{FPGA}
@ -215,6 +193,8 @@
Communication between devices is implemented using 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on the Kasli 2.0. Appropriate SFP transceivers must be plugged inside the corresponding SFP cages. Each SFP connector possesses an indicator LED.
Transceiver maximum speed is 6.6 Gb/s\footnote{\url{https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/high-speed-serial.html}}. DRTIO is normally run at 2.5 Gb/s with 8b10b encoding.
\subsection{Upstream connection}
A Kasli 2.0 board must acquire an upstream connection through the \texttt{SFP0} slot.
@ -223,11 +203,11 @@
\item \textbf{Standalone/Master} \\
An Ethernet-capable SFP transceiver should be inserted into the \texttt{SFP0} slot. Typically, a 10000Base-X RJ45 SFP module is used, with an network-connected Ethernet cable attached to the module.
\item \textbf{Satellite} \\
The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable connection with SFP transceivers.
The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable or fibre connection with SFP transceivers.
\end{itemize}
\subsection{Downstream connection}
Kasli 2.0 supports up to 3 DRTIO satellite connections per device. Any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be used.
Kasli 2.0 supports up to 3 DRTIO satellite connections per device. Any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be used. The destination on port \texttt{SFPn} normally receives the destination number \texttt{n}.
\clockingsection{Kasli 2.0}{FPGA}
@ -251,8 +231,6 @@
\coresysdesc
\newpage
\coredevicecode{Kasli 2.0 1124 carrier}
\ordersection{1124 Carrier Kasli 2.0}

49
1125.tex
View File

@ -5,7 +5,7 @@
\title{1125 Carrier Kasli-SoC}
\author{M-Labs Limited}
\date{December 2024}
\revision{Revision 0} % WIP
\revision{Revision 1} % potentially publishable pending whether block diagram is necessary
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
\begin{document}
@ -15,9 +15,9 @@
\begin{itemize}
\item{RJ45 10/100/1000T Ethernet connector}
\item{4 SFP 6Gb/s slots for DRTIO}
\item{4 SFP 12Gb/s slots for DRTIO at 2.5Gb/s}
\item{12 EEM ports for daughtercards}
\item{Xilinx Zynq-7 SoC with Kintex-7 FPGA}
\item{Xilinx Zynq-7000 SoC with Kintex-7 FPGA}
\item{SD card flash memory}
\end{itemize}
@ -32,11 +32,11 @@
\section{General Description}
The 1125 Kasli-SoC Carrier card is an 8hp EEM module, designed to run ARTIQ-Zynq kernels sent over the network from a host machine. Kasli-SoC is built around a Xilinx Zynq-7 SoC, allowing it to run more complex computations at high speed than its sister card 1124 Kasli 2.0. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up four SFP connections for comunications with other carriers. A dedicated Ethernet port is used for communications with the host.
The 1125 Kasli-SoC Carrier card is an 8hp EEM module, designed to run ARTIQ-Zynq kernels sent over the network from a host machine. Kasli-SoC is built around a Xilinx Zynq-7000 SoC, capable of running more complex computations at high speed than its sister card 1124 Kasli 2.0. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up four SFP connections for comunications with other carriers. A dedicated Ethernet port is used for communications with the host.
Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.
4 SFP 6Gb/s slots are provided. These can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli 2.0, Kasli-SoC) as satellite cards, capable of running subkernels or distributing commands from the \mbox{DRTIO} master.
4 SFP 12Gb/s slots are provided. These can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli or other Kasli-SoCs) as satellite cards, capable of running subkernels or relaying commands to a larger number of peripherals.
% Switch to next column
\vfill\break
@ -58,29 +58,16 @@
\section{Electrical Specifications}
% DATASHEET: https://docs.amd.com/v/u/en-US/ds190-Zynq-7000-Overview
External clock parameters are derived based on the internal termination specified in
UG471\footnote{\label{ug471}\url{https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO}}
and the voltage range specified in
DS191\footnote{\label{ds191}\url{https://docs.amd.com/v/u/en-US/ds191-XC7Z030-XC7Z045-data-sheet}}. These figures account for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}\url{https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}}).
\textbf{TODO}
\begin{table}[h]
\centering
\begin{threeparttable}
\caption{Recommended Operating Conditions}
\begin{tabularx}{0.85\textwidth}{l | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
Power is to be supplied through the barrel connector in the front panel, size 5.5 mm OD, 2.5 mm ID, and is passed on to daughtercards through the EEM connections. Locking barrel connectors are supported.
\spectable
\section{SoC}
Kasli-SoC features a XC7Z030 Xilinx Zynq-7000 System-on-Chip with a Kintex-7 FGPA and an Cortex-A9 dual-core processor to facilitate high-speed real-time control of inputs and outputs. The use of the SoC allows for more complex computations at higher speed than Kasli 2.0's purely on-FPGA CPU. Usually, the SoC is flashed with firmware and gateware binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with the ability to control other Sinara EEMs and run ARTIQ experiment kernels.
Kasli-SoC features a XC7Z030-3FFG676E Xilinx Zynq-7000 System-on-Chip with a Kintex-7 FGPA and an Cortex-A9 dual-core processor to facilitate high-speed real-time control of inputs and outputs. The use of the SoC allows for more complex computations at higher speed than Kasli 2.0's purely on-FPGA CPU. Usually, the SoC is flashed with firmware and gateware binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with the ability to control other Sinara EEMs and run ARTIQ experiment kernels.
A micro-USB located on the front panel is equipped for JTAG, I2C, and UART serial output. The serial interface runs at 115200bps 8-N-1.
@ -92,7 +79,9 @@
\section{Communication Interfaces}
Communication between core devices is implemented with 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on 1125 Kasli-SoC. Appropriate SFP transceivers must be plugged inside the corresponding SFP cages. Each SFP connector possesses an indicator LED.
Communication between core devices is implemented with 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on 1125 Kasli-SoC. Each SFP connector possesses an indicator LED.
Transceiver maximum speed is 12.5 Gb/s\footnote{\url{https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/high-speed-serial.html}}. DRTIO is normally run at 2.5 Gb/s with 8b10b encoding.
Additionally, a RJ45 10/100/1000T Ethernet port is featured for network connection to a host machine.
@ -102,14 +91,16 @@
\item \textbf{Standalone/Master} \\
A network-connected Ethernet cable should be attached the front panel Ethernet port to enable communication with a host machine.
\item \textbf{Satellite} \\
Satellites must acquire an upstream connection to another satellite or the master. The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable connection with SFP transceivers.
Satellites must acquire an upstream connection to another satellite or the master. The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable or fibre connection with SFP transceivers.
\end{itemize}
\subsection{Downstream connection}
Kasli-SoC supports up to 4 DRTIO satellite connections per device. Any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be freely used. On a master device, \texttt{SFP0} can also be used for a downstream connection, though some care is required with the enusing DRTIO destination numbers.
Kasli-SoC supports up to 4 DRTIO satellite connections per device. Any of the 4 downstream SFP ports (i.e. \texttt{SFP0}, \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be freely used. Port \texttt{SFPn} normally receives the destination number \texttt{n + 1}.
\clockingsection{Kasli-SoC}{SoC}
\newpage
\section{Configuring Boot Mode}
Kasli-SoC is capable of booting either remotely, over JTAG USB, or directly from the SD card. See the ARTIQ manual for more instructions on how to correctly flash and boot a core device. Boot mode must be configured by flipping physical switches on the board. The boot mode DIP switches are located in the middle of the board. To boot from USB, flip both switches towards the label \texttt{JTAG}. To boot from the SD card, flip both switches towards the label \texttt{SD}.
@ -126,7 +117,7 @@
\section{User LEDs}
Kasli-SoC designates two user LEDs for debugging purposes. Both are located on the PCB. The first, labeled \texttt{USER0}, can be found at the very bottom left of the PCB, below the SFP cage. The second, labeled \texttt{LD1}, can be found at the top left, roughly behind the micro-USB port.
Kasli-SoC designates two user LEDs for debugging purposes. One is located on the PCB; it can be found at the very bottom left of the board, below the SFP cage, labeled \texttt{USER0}. The second is located on the front panel, besides the Ethernet port, labeled \texttt{L1}.
\sysdescsection
@ -144,8 +135,6 @@
\coresysdesc
\newpage
\coredevicecode{1125 Kasli-SoC carrier}
\ordersection{1125 Carrier Kasli-SoC}

31
shared/coredevice.tex
View File

@ -1,3 +1,30 @@
\newcommand{\spectable} {
\begin{table}[h]
\centering
\begin{threeparttable}
\caption{Recommended Operating Conditions}
\begin{tabularx}{0.85\textwidth}{l | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Clock input & & & & &\\
\hspace{3mm} Input frequency & & 125 & & MHz & Si5324 synthesizer bypassed \\
\cline{2-6}
% 100R termination & 100/350/600 mV differential input after the transformer.
& \multicolumn{3} {c|}{10/80/100/125} & MHz & RTIO clock synthesized from input \\
\cline{2-6}
\hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm & \\
\hline
Power supply rating & \multicolumn{4}{c|}{12V, 5A} & \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
Power is to be supplied either through the barrel connector in the front panel (size 5.5 mm OD, 2.5 mm ID) or the Molex connector at the back of the card (compatible with e.g. Sinara 1106 EEM AC Power Module). It is passed on to daughtercards through the EEM connections. Locking barrel connectors are supported.
}
\newcommand{\artiqsection} {
\section{Firmware/ARTIQ}
@ -34,11 +61,11 @@
\hline
RTIO frequency & Configuration & Clock generation \\ \hline
100 MHz & \texttt{int\char`_100} & internal crystal oscillator using PLL, 100 MHz output \\ \hline
\multirow{4}{*}{125 MHz} & \texttt{int\char`_125} & internal crystal oscillator using PLL, 125 MHz output (default) \\ \cline{2-3}
\multirow{5}{*}{125 MHz} & \texttt{int\char`_125} & internal crystal oscillator using PLL, 125 MHz output (default) \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_10to125} & external 10 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_80to125} & external 80 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_100to125} & external 100 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_125to125} & external 125 MHz reference using PLL, 125 MHz output \\ \hline
150 MHz & \texttt{int\char`_150} & internal crystal oscillator using PLL, 150 MHz output \\ \hline
\end{tabular}
\end{table}