diff --git a/2118-2128.tex b/2118-2128.tex
index dd97012..92f233e 100644
--- a/2118-2128.tex
+++ b/2118-2128.tex
@@ -341,6 +341,7 @@ The card support a minimum pulse width of 3ns.
 
 \section{Electrical Specifications}
 All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
+Pulse width distortion \& peak jitters are based on the isolator IC (SI8651BB-B-IS1), other specifications are based on the bus transceivers IC (SN74BCT25245DW).
 
 \begin{table}[h]
 \begin{threeparttable}
diff --git a/2238.tex b/2238.tex
index 01646ff..81dae02 100644
--- a/2238.tex
+++ b/2238.tex
@@ -473,6 +473,9 @@ This card can achieve higher speed and lower jitter than the isolated 2118/2128
 \onecolumn
 
 \section{Electrical Specifications}
+
+Both recommended operating conditions and electrical characteristics are based on the datasheet of the bus transceivers IC (74LVT162245MTD).
+
 \begin{table}[h]
 \begin{threeparttable}
 \caption{Recommended Operating Conditions}
@@ -493,7 +496,6 @@ This card can achieve higher speed and lower jitter than the isolated 2118/2128
 \end{threeparttable}
 \end{table}
 The recommended operating temperature is $-40\degree C \leq T_A \leq 85\degree C$.
-
 All specifications are in the recommended operating temperature range unless otherwise noted.
 
 \begin{table}[h]
@@ -541,7 +543,7 @@ IO direction switches partly decides the IO direction of each bank.
 \columnbreak
 \begin{center}
     \centering
-    \includegraphics[height=1.8in]{mcx_ttl_switches.jpg}
+    \includegraphics[height=1.7in]{mcx_ttl_switches.jpg}
     \captionof{figure}{Position of switches}
 \end{center}
 \end{multicols}
diff --git a/2245.tex b/2245.tex
index f67de2b..7110d15 100644
--- a/2245.tex
+++ b/2245.tex
@@ -334,6 +334,9 @@ Only shielded Ethernet Cat-6 cables should be connected.
 \onecolumn
 
 \section{Electrical Specifications}
+
+Information in this section is based on the datasheet of the repeaters IC (FIN1101K8X).
+
 The Absolute Maximum Ratings are thorse values beyond which damage to the device may occur
 Other specifications should be met without exception.
 
@@ -398,10 +401,6 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
     Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
     \hline
     Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended Input Voltage \\
-    \hline
-    Input capacitance & $C_{IN}$ & & 2.0 & & pF & \\
-    \hline
-    Output capacitance & $C_{OUT}$ & & 2.6 & & pF & \\
     \thickhline
 \end{tabularx}
 \end{threeparttable}
@@ -410,6 +409,7 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
 \newpage
 
 All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise specified.
+Information regarding propagation is not applicable due to the lack of trace length matching.
 
 \begin{table}[h]
 \begin{threeparttable}
@@ -419,19 +419,13 @@ All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 30
     \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
     \textbf{Unit} & \textbf{Conditions} \\
     \hline
-    Differential Propagation delay & \multirow{2}{*}{$t_{PLHD}$} & \multirow{2}{*}{0.75} & \multirow{2}{*}{1.1} & \multirow{2}{*}{1.75} & \multirow{2}{*}{ns} & 100\textOmega~ between +/- outputs,\\
-    (LOW-to-HIGH) & & & & & & 5pF between each output and GND,\\
-    \cline{0-5}
-    Differential Propagation delay & \multirow{2}{*}{$t_{PHLD}$} & \multirow{2}{*}{0.75} & \multirow{2}{*}{1.1} & \multirow{2}{*}{1.75} & \multirow{2}{*}{ns} & $200 mV \leq V_{ID} \leq 450 mV$,\\
-    (HIGH-to-LOW) & & & & & & recommended $V_{IC}$,\\
-    \cline{0-5}
     Differential Output Rise Time & \multirow{2}{*}{$t_{TLHD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & duty Cycle = 50\%.\\
     (20\% to 80\%) & & & & & & \\
     \cline{0-5}
     Differential Output Fall Time & \multirow{2}{*}{$t_{THLD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
     (80\% to 20\%) & & & & & & \\
     \cline{0-5}
-    Pulse skew & $t_{SK(P)}$ & & 0.01 & 0.2 & ns & \\
+    Pulse width distortion & $PWD$ & & 0.01 & 0.2 & ns & \\
     \hline
     LVDS data jitter, & \multirow{2}{*}{$t_{DJ}$} & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
     deterministic & & & & & & 800 Mbps\\