architeuthis
/
assembly
forked from sinara-hw/assembly
1
0
Fork 0
Code Pull Requests Activity

Fix urukuls sync misleading information 

Signed-off-by: Egor Savkin <es@m-labs.hk>
This commit is contained in:
Egor Savkin 2023-07-25 11:12:23 +08:00
parent c6cb876c1c
commit f45c292a66
1 changed files with 5 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/hw/urukul.md
View File

@ -24,13 +24,11 @@ Check if [SUServo](./suservo.md) is enabled/disabled respective to customer need
### Synchronization
Synchronization option in the JSON refers to the phase synchronization between the outputs, and can be used only on AD9910 variants and
only with 125 MHz clock source provided from Kasli/Kasli-SoC (may be relayed through the Clocker board).
The phase sync works only within one Urukul board, though the phase shift between Urukuls may be [predictable](https://github.com/m-labs/artiq/issues/1692#issuecomment-994439589).
Even though it is widely-desirable feature, there are drawbacks of this preventing from enabling by default:
1. The resulting signal is more noisy, which can be observed [previously](https://github.com/sinara-hw/Urukul/issues/64).
2. Phase sync process takes time and sometimes fails
3. ???
Phase synchronization enables phase control from Kasli/Kasli-SoC with an absolute phase reference, i.e. you can use the phase control API in the coredevice driver.
Without synchronization the phase between Urukuls will not drift, but it can change across reboots, and the phase control API cannot be used.
Synchronization requires Kasli and Urukul to be clocked from the same oscillator with <<1ns noise, otherwise the synchronization may fail, and that's
why this feature is disabled by default.
There is no intrinsic impact on Urukul output phase noise and the synchronization process is quick and reliable when done correctly.
## Testing