forked from M-Labs/artiq-zynq
add RTIO syscalls
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986c4e9327
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ce6c89e343
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@ -30,6 +30,12 @@ version = "0.1.26"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "036b035e9ebcd705affece16319223d19f229e2358be6e3b7b094e57193312e6"
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[[package]]
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name = "cslice"
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version = "0.3.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "0f8cb7306107e4b10e64994de6d3274bd08996a7c1322a27b86482392f96be0a"
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[[package]]
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name = "dyld"
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version = "0.1.0"
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@ -154,6 +160,7 @@ checksum = "bd7a31eed1591dcbc95d92ad7161908e72f4677f8fabf2a32ca49b4237cbf211"
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name = "runtime"
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version = "0.1.0"
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dependencies = [
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"cslice",
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"dyld",
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"libasync",
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"libboard_zynq",
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@ -12,6 +12,7 @@ default = ["target_zc706"]
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[dependencies]
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num-traits = { version = "0.2", default-features = false }
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num-derive = "0.3"
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cslice = "0.3"
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libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libsupport_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libasync = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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@ -13,6 +13,7 @@ use libsupport_zynq::ram;
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mod pl;
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mod rtio;
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mod network;
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fn identifier_read(buf: &mut [u8]) -> &str {
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@ -0,0 +1,173 @@
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use core::ptr::{read_volatile, write_volatile};
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use cslice::CSlice;
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use libboard_zynq::println;
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use crate::pl::csr;
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pub const RTIO_O_STATUS_WAIT: u8 = 1;
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pub const RTIO_O_STATUS_UNDERFLOW: u8 = 2;
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pub const RTIO_O_STATUS_DESTINATION_UNREACHABLE: u8 = 4;
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pub const RTIO_I_STATUS_WAIT_EVENT: u8 = 1;
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pub const RTIO_I_STATUS_OVERFLOW: u8 = 2;
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pub const RTIO_I_STATUS_WAIT_STATUS: u8 = 4;
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pub const RTIO_I_STATUS_DESTINATION_UNREACHABLE: u8 = 8;
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#[repr(C)]
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pub struct TimestampedData {
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timestamp: i64,
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data: i32,
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}
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pub extern fn init() {
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// TODO
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}
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pub extern fn get_destination_status(destination: i32) -> bool {
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// TODO
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destination == 0
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}
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pub extern fn get_counter() -> i64 {
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unsafe {
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csr::rtio::counter_update_write(1);
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csr::rtio::counter_read() as i64
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}
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}
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// writing the LSB of o_data (offset=0) triggers the RTIO write
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#[inline(always)]
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pub unsafe fn rtio_o_data_write(offset: usize, data: u32) {
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write_volatile(
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csr::rtio::O_DATA_ADDR.offset((csr::rtio::O_DATA_SIZE - 1 - offset) as isize),
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data);
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}
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#[inline(always)]
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pub unsafe fn rtio_i_data_read(offset: usize) -> u32 {
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read_volatile(
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csr::rtio::I_DATA_ADDR.offset((csr::rtio::I_DATA_SIZE - 1 - offset) as isize))
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}
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#[inline(never)]
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unsafe fn process_exceptional_status(channel: i32, status: u8) {
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let timestamp = *(csr::rtio::NOW_HI_ADDR as *const i64);
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if status & RTIO_O_STATUS_WAIT != 0 {
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while csr::rtio::o_status_read() & RTIO_O_STATUS_WAIT != 0 {}
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}
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if status & RTIO_O_STATUS_UNDERFLOW != 0 {
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println!("RTIO underflow at {0} mu, channel {1}, slack {2} mu",
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timestamp, channel as i64, timestamp - get_counter());
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}
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if status & RTIO_O_STATUS_DESTINATION_UNREACHABLE != 0 {
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println!("RTIO destination unreachable, output, at {0} mu, channel {1}",
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timestamp, channel as i64);
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}
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}
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pub extern fn output(target: i32, data: i32) {
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unsafe {
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csr::rtio::target_write(target as u32);
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// writing target clears o_data
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rtio_o_data_write(0, data as _);
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let status = csr::rtio::o_status_read();
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if status != 0 {
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process_exceptional_status(target >> 8, status);
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}
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}
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}
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pub extern fn output_wide(target: i32, data: CSlice<i32>) {
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unsafe {
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csr::rtio::target_write(target as u32);
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// writing target clears o_data
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for i in (0..data.len()).rev() {
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rtio_o_data_write(i, data[i] as _)
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}
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let status = csr::rtio::o_status_read();
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if status != 0 {
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process_exceptional_status(target >> 8, status);
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}
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}
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}
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pub extern fn input_timestamp(timeout: i64, channel: i32) -> i64 {
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unsafe {
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csr::rtio::target_write((channel as u32) << 8);
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csr::rtio::i_timeout_write(timeout as u64);
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let mut status = RTIO_I_STATUS_WAIT_STATUS;
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while status & RTIO_I_STATUS_WAIT_STATUS != 0 {
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status = csr::rtio::i_status_read();
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}
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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csr::rtio::i_overflow_reset_write(1);
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println!("RTIO input overflow on channel {0}",
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channel as i64);
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}
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if status & RTIO_I_STATUS_WAIT_EVENT != 0 {
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return -1
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}
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if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
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println!("RTIO destination unreachable, input, on channel {0}",
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channel as i64);
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}
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csr::rtio::i_timestamp_read() as i64
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}
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}
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pub extern fn input_data(channel: i32) -> i32 {
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unsafe {
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csr::rtio::target_write((channel as u32) << 8);
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csr::rtio::i_timeout_write(0xffffffff_ffffffff);
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let mut status = RTIO_I_STATUS_WAIT_STATUS;
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while status & RTIO_I_STATUS_WAIT_STATUS != 0 {
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status = csr::rtio::i_status_read();
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}
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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csr::rtio::i_overflow_reset_write(1);
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println!("RTIO input overflow on channel {0}",
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channel as i64);
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}
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if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
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println!("RTIO destination unreachable, input, on channel {0}",
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channel as i64);
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}
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rtio_i_data_read(0) as i32
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}
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}
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pub extern fn input_timestamped_data(timeout: i64, channel: i32) -> TimestampedData {
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unsafe {
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csr::rtio::target_write((channel as u32) << 8);
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csr::rtio::i_timeout_write(timeout as u64);
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let mut status = RTIO_I_STATUS_WAIT_STATUS;
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while status & RTIO_I_STATUS_WAIT_STATUS != 0 {
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status = csr::rtio::i_status_read();
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}
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if status & RTIO_I_STATUS_OVERFLOW != 0 {
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csr::rtio::i_overflow_reset_write(1);
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println!("RTIO input overflow on channel {0}",
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channel as i64);
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}
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if status & RTIO_I_STATUS_WAIT_EVENT != 0 {
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return TimestampedData { timestamp: -1, data: 0 }
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}
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if status & RTIO_I_STATUS_DESTINATION_UNREACHABLE != 0 {
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println!("RTIO destination unreachable, input, on channel {0}",
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channel as i64);
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}
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TimestampedData {
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timestamp: csr::rtio::i_timestamp_read() as i64,
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data: rtio_i_data_read(0) as i32
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}
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}
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}
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