forked from M-Labs/artiq-zynq
Add grabber module
(cherry picked from commit b768d5648c
)
Signed-off-by: Egor Savkin <es@m-labs.hk>
This commit is contained in:
parent
00c5ee01b0
commit
9b76896edd
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@ -77,7 +77,7 @@ class RTIOCRG(Module, AutoCSR):
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MultiReg(pll_locked, self.pll_locked.status)
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]
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eem_iostandard_dict = {
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0: "LVDS_25",
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1: "LVDS_25",
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@ -114,6 +114,7 @@ class SMAClkinForward(Module):
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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self.acpki = acpki
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sys_clk_freq = 125e6
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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@ -142,6 +143,7 @@ class GenericStandalone(SoCCore):
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self.ps7.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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fix_serdes_timing_path(platform)
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self.config["CLOCK_FREQUENCY"] = int(sys_clk_freq)
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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@ -226,6 +228,7 @@ class GenericMaster(SoCCore):
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pads=data_pads,
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.config["CLOCK_FREQUENCY"] = int(sys_clk_freq)
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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@ -330,7 +333,7 @@ class GenericMaster(SoCCore):
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class GenericSatellite(SoCCore):
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def __init__(self, description, acpki=False):
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sys_clk_freq = 125e6
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sys_clk_freq = 125e6
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rtio_clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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@ -353,7 +356,7 @@ class GenericSatellite(SoCCore):
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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@ -458,6 +461,7 @@ class GenericSatellite(SoCCore):
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rtio_clk_period = 1e9/rtio_clk_freq
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.config["CLOCK_FREQUENCY"] = int(sys_clk_freq)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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@ -485,7 +489,7 @@ class GenericSatellite(SoCCore):
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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# no RTIO CRG here
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self.submodules.virtual_leds = virtual_leds.VirtualLeds()
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self.csr_devices.append("virtual_leds")
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@ -0,0 +1,163 @@
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use log::info;
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use crate::pl::csr;
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#[derive(PartialEq, Clone, Copy)]
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enum State {
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Reset,
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ExitReset,
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Lock,
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Align,
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Watch,
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}
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#[derive(Clone, Copy)]
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struct Info {
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state: State,
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frame_size: (u16, u16),
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}
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static mut INFO: [Info; csr::GRABBER_LEN] = [Info {
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state: State::Reset,
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frame_size: (0, 0),
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}; csr::GRABBER_LEN];
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fn get_pll_reset(g: usize) -> bool {
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unsafe { (csr::GRABBER[g].pll_reset_read)() != 0 }
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}
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fn set_pll_reset(g: usize, reset: bool) {
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let val = if reset { 1 } else { 0 };
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unsafe { (csr::GRABBER[g].pll_reset_write)(val) }
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}
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fn pll_locked(g: usize) -> bool {
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unsafe { (csr::GRABBER[g].pll_locked_read)() != 0 }
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}
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fn clock_pattern_ok(g: usize) -> bool {
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unsafe { (csr::GRABBER[g].clk_sampled_read)() == 0b1100011 }
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}
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fn clock_pattern_ok_filter(g: usize) -> bool {
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for _ in 0..128 {
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if !clock_pattern_ok(g) {
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return false;
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}
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}
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true
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}
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fn phase_shift(g: usize, direction: u8) {
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unsafe {
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(csr::GRABBER[g].phase_shift_write)(direction);
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while (csr::GRABBER[g].phase_shift_done_read)() == 0 {}
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}
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}
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fn clock_align(g: usize) -> bool {
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while clock_pattern_ok_filter(g) {
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phase_shift(g, 1);
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}
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phase_shift(g, 1);
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let mut count = 0;
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while !clock_pattern_ok_filter(g) {
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phase_shift(g, 1);
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count += 1;
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if count > 1024 {
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return false;
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}
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}
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let mut window = 1;
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phase_shift(g, 1);
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while clock_pattern_ok_filter(g) {
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phase_shift(g, 1);
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window += 1;
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}
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for _ in 0..window / 2 {
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phase_shift(g, 0);
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}
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true
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}
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fn get_last_pixels(g: usize) -> (u16, u16) {
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unsafe { ((csr::GRABBER[g].last_x_read)(), (csr::GRABBER[g].last_y_read)()) }
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}
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fn get_video_clock(g: usize) -> u32 {
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let freq_count = unsafe { (csr::GRABBER[g].freq_count_read)() } as u32;
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2 * freq_count * (csr::CONFIG_CLOCK_FREQUENCY / 1000) / (511 * 1000)
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}
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pub fn tick() {
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for g in 0..csr::GRABBER.len() {
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let next = match unsafe { INFO[g].state } {
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State::Reset => {
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set_pll_reset(g, true);
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unsafe {
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INFO[g].frame_size = (0, 0);
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}
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State::ExitReset
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}
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State::ExitReset => {
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if get_pll_reset(g) {
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set_pll_reset(g, false);
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State::Lock
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} else {
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State::ExitReset
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}
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}
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State::Lock => {
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if pll_locked(g) {
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info!("grabber{} locked: {}MHz", g, get_video_clock(g));
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State::Align
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} else {
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State::Lock
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}
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}
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State::Align => {
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if pll_locked(g) {
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if clock_align(g) {
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info!("grabber{} alignment success", g);
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State::Watch
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} else {
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info!("grabber{} alignment failure", g);
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State::Reset
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}
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} else {
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info!("grabber{} lock lost", g);
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State::Reset
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}
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}
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State::Watch => {
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if pll_locked(g) {
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if clock_pattern_ok(g) {
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let last_xy = get_last_pixels(g);
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if last_xy != unsafe { INFO[g].frame_size } {
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// x capture is on ~LVAL which is after
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// the last increment on DVAL
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// y capture is on ~FVAL which coincides with the
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// last increment on ~LVAL
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info!("grabber{} frame size: {}x{}", g, last_xy.0, last_xy.1 + 1);
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unsafe { INFO[g].frame_size = last_xy }
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}
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State::Watch
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} else {
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info!("grabber{} alignment lost", g);
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State::Reset
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}
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} else {
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info!("grabber{} lock lost", g);
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State::Reset
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}
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}
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};
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unsafe {
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INFO[g].state = next;
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}
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}
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}
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@ -29,6 +29,8 @@ pub mod drtioaux_async;
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pub mod mem;
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#[cfg(feature = "target_kasli_soc")]
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pub mod io_expander;
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#[cfg(has_grabber)]
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pub mod grabber;
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use core::{cmp, str};
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use libboard_zynq::slcr;
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@ -110,6 +110,21 @@ async fn io_expanders_service(
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.expect("I2C I/O expander #1 service failed");
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}
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}
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#[cfg(has_grabber)]
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mod grabber {
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use libasync::delay;
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use libboard_artiq::grabber;
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use libboard_zynq::time::Milliseconds;
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use crate::GlobalTimer;
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pub async fn grabber_thread(timer: GlobalTimer) {
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let mut countdown = timer.countdown();
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loop {
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grabber::tick();
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delay(&mut countdown, Milliseconds(200)).await;
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}
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}
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}
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static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];
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#[no_mangle]
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@ -168,6 +183,9 @@ pub fn main_core0() {
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task::spawn(report_async_rtio_errors());
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#[cfg(has_grabber)]
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task::spawn(grabber::grabber_thread(timer));
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#[cfg(feature = "target_kasli_soc")]
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task::spawn(io_expanders_service(
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RefCell::new(i2c_bus),
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@ -20,6 +20,8 @@ extern crate alloc;
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use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio};
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use libsupport_zynq::ram;
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#[cfg(has_grabber)]
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use libboard_artiq::grabber;
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#[cfg(has_si5324)]
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use libboard_artiq::si5324;
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#[cfg(feature = "target_kasli_soc")]
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@ -417,6 +419,8 @@ fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) {
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if now > ts_ms {
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ts_ms = now + Milliseconds(200);
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*ts = ts_ms.0;
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#[cfg(has_grabber)]
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grabber::tick();
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}
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}
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