forked from M-Labs/artiq-zynq
core1: added cache flush and barriers.
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@ -5,7 +5,12 @@ use alloc::borrow::ToOwned;
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use log::{debug, info, error};
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use cslice::CSlice;
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use libcortex_a9::{enable_fpu, cache::{dcci_slice, iciallu}, sync_channel};
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use libcortex_a9::{
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enable_fpu,
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cache::{dcci_slice, iciallu, bpiall},
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asm::{dsb, isb},
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sync_channel
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};
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use dyld::{self, Library};
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use crate::eh_artiq;
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use super::{
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@ -92,7 +97,11 @@ impl KernelImage {
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// Flush data cache entries for the image in DDR, including
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// Memory/Instruction Synchronization Barriers
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dcci_slice(self.library.image.data);
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dsb();
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iciallu();
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bpiall();
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dsb();
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isb();
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(mem::transmute::<u32, fn()>(self.__modinit__))();
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